Commit b2bfe0fa authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Vinod Koul
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soundwire: qcom: adding support for v3.1.0 



Add support for controller version v3.1.0, which has changes in
register layout and some register fields compared to v2.0.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Tested-by: Alexey Klimov <alexey.klimov@linaro.org> # sm8550
Link: https://patch.msgid.link/20250912083225.228778-8-srinivas.kandagatla@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 66eca4b7

drivers/soundwire/qcom.c

+36 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define SWRM_VERSION_1_5_1					0x01050001

#define SWRM_VERSION_1_7_0					0x01070000

#define SWRM_VERSION_2_0_0					0x02000000

#define SWRM_VERSION_3_1_0					0x03010000

#define SWRM_COMP_HW_VERSION					0x00

#define SWRM_COMP_CFG_ADDR					0x04

#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK			BIT(1)
@@ -40,6 +41,9 @@ 
#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH				GENMASK(19, 15)

#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK			GENMASK(4, 0)

#define SWRM_COMP_PARAMS_DIN_PORTS_MASK				GENMASK(9, 5)

#define SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH			GENMASK(17, 10)

#define SWRM_V3_COMP_PARAMS_RD_FIFO_DEPTH			GENMASK(23, 18)



#define SWRM_COMP_MASTER_ID					0x104

#define SWRM_V1_3_INTERRUPT_STATUS				0x200

#define SWRM_V2_0_INTERRUPT_STATUS				0x5000
@@ -296,6 +300,32 @@ static const struct qcom_swrm_data swrm_v2_0_data = { 
	.reg_layout = swrm_v2_0_reg_layout,

};



static const unsigned int swrm_v3_0_reg_layout[] = {

	[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,

	[SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,

	[SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */

	[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,

	[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,

	[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,

	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,

	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,

	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,

	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1224,

	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1228,

	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x122c,

	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1230,

	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1234,

	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1238,

	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x123c,

};



static const struct qcom_swrm_data swrm_v3_0_data = {

	.default_rows = 50,

	.default_cols = 16,

	.sw_clk_gate_required = true,

	.max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,

	.reg_layout = swrm_v3_0_reg_layout,

};

#define to_qcom_sdw(b)	container_of(b, struct qcom_swrm_ctrl, bus)



static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
@@ -919,6 +949,10 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 
	swrm_wait_for_frame_gen_enabled(ctrl);

	ctrl->slave_status = 0;

	ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);



	if (ctrl->version >= SWRM_VERSION_3_1_0)

		ctrl->wr_fifo_depth = FIELD_GET(SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH, val);

	else

		ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);



	return 0;
@@ -1785,6 +1819,7 @@ static const struct of_device_id qcom_swrm_of_match[] = { 
	{ .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },

	{ .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },

	{ .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },

	{ .compatible = "qcom,soundwire-v3.1.0", .data = &swrm_v3_0_data },

	{/* sentinel */},

};