Commit b330f148 authored by Biju Das's avatar Biju Das Committed by Tomi Valkeinen
Browse files

drm: renesas: rz-du: Add RZ/G2UL DU Support 



The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI interface and supports a maximum resolution of WXGA along
with 2 RPFs to support the blending of two picture layers and raster
operations (ROPs).

The DU module is connected to VSPD. Add RZ/G2UL DU support.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822162320.5084-3-biju.das.jz@bp.renesas.com
parent 2ef7cb1c

drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c

+7 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "rzg2l_du_vsp.h"



#define DU_MCR0			0x00

#define DU_MCR0_DPI_OE		BIT(0)

#define DU_MCR0_DI_EN		BIT(8)



#define DU_DITR0		0x10
@@ -216,9 +217,14 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc) 


static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)

{

	struct rzg2l_du_crtc_state *rstate = to_rzg2l_crtc_state(rcrtc->crtc.state);

	struct rzg2l_du_device *rcdu = rcrtc->dev;

	u32 val = DU_MCR0_DI_EN;



	writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);

	if (rstate->outputs & BIT(RZG2L_DU_OUTPUT_DPAD0))

		val |= DU_MCR0_DPI_OE;



	writel(start ? val : 0, rcdu->mmio + DU_MCR0);

}



static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)

drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c

+11 −0
Original line number Diff line number Diff line
@@ -25,6 +25,16 @@ 
 * Device Information

 */



static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {

	.channels_mask = BIT(0),

	.routes = {

		[RZG2L_DU_OUTPUT_DPAD0] = {

			.possible_outputs = BIT(0),

			.port = 0,

		},

	},

};



static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {

	.channels_mask = BIT(0),

	.routes = {
@@ -40,6 +50,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { 
};



static const struct of_device_id rzg2l_du_of_table[] = {

	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },

	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },

	{ /* sentinel */ }

};

drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c

+2 −1
Original line number Diff line number Diff line
@@ -183,7 +183,8 @@ static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu) 


		/* Find the output route corresponding to the port number. */

		for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {

			if (rcdu->info->routes[i].port == ep.port) {

			if (rcdu->info->routes[i].possible_outputs &&

			    rcdu->info->routes[i].port == ep.port) {

				output = i;

				break;

			}