Commit b3a663f0 authored by Wenli Looi's avatar Wenli Looi Committed by Kalle Valo
Browse files

wifi: ath9k: remove most hidden macro dependencies on ah 



Adds an explicit _ah parameter to most macros that previously had a
hidden dependency on ah. This makes the code more compliant with the
style guide.

This change does not appear to affect the final binary.

Signed-off-by: default avatarWenli Looi <wlooi@ucalgary.ca>
Acked-by: default avatarToke Høiland-Jørgensen <toke@toke.dk>
Signed-off-by: default avatarKalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/c8369317-cf84-f0e3-fe8-9b6e22e43a6a@ucalgary.ca
parent 950b43f8

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+5 −5
Original line number Diff line number Diff line
@@ -1277,13 +1277,13 @@ static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 


static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array)

{

#define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x))

	ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]);

	ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l],

#define CCK_DELTA(_ah, x) ((OLC_FOR_AR9280_20_LATER(_ah)) ? max((x) - 2, 0) : (x))

	ah->tx_power[0] = CCK_DELTA(ah, rate_array[rate1l]);

	ah->tx_power[1] = CCK_DELTA(ah, min(rate_array[rate2l],

					rate_array[rate2s]));

	ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l],

	ah->tx_power[2] = CCK_DELTA(ah, min(rate_array[rate5_5l],

					rate_array[rate5_5s]));

	ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l],

	ah->tx_power[3] = CCK_DELTA(ah, min(rate_array[rate11l],

					rate_array[rate11s]));

#undef CCK_DELTA

}

drivers/net/wireless/ath/ath9k/ar9002_calib.c

+15 −15
Original line number Diff line number Diff line
@@ -659,9 +659,9 @@ static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset) 


static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)

{

	if (OLC_FOR_AR9287_10_LATER)

	if (OLC_FOR_AR9287_10_LATER(ah))

		ar9287_hw_olc_temp_compensation(ah);

	else if (OLC_FOR_AR9280_20_LATER)

	else if (OLC_FOR_AR9280_20_LATER(ah))

		ar9280_hw_olc_temp_compensation(ah);

}
@@ -672,7 +672,7 @@ static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, 
	bool nfcal, nfcal_pending = false, percal_pending;

	int ret;



	nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);

	nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF);

	if (ah->caldata) {

		nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags);

		if (longcal)		/* Remember to not miss */
@@ -752,11 +752,11 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
	if (IS_CHAN_HT20(chan)) {

		REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);

		REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);

		REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

		REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),

			    AR_PHY_AGC_CONTROL_FLTR_CAL);

		REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);

		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,

		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah),

				  AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {

			ath_dbg(common, CALIBRATE,

				"offset calibration failed to complete in %d ms; noisy environment?\n",
@@ -768,10 +768,10 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

	}

	REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);

	REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

	if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);

	if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL,

			  0, AH_WAIT_TIMEOUT)) {

		ath_dbg(common, CALIBRATE,

			"offset calibration failed to complete in %d ms; noisy environment?\n",
@@ -781,7 +781,7 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) 


	REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

	REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);

	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);



	return true;

}
@@ -857,17 +857,17 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
			if (!AR_SREV_9287_11_OR_LATER(ah))

				REG_CLR_BIT(ah, AR_PHY_ADC_CTL,

					    AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,

			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),

				    AR_PHY_AGC_CONTROL_FLTR_CAL);

		}



		/* Calibrate the AGC */

		REG_WRITE(ah, AR_PHY_AGC_CONTROL,

			  REG_READ(ah, AR_PHY_AGC_CONTROL) |

		REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),

			  REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) |

			  AR_PHY_AGC_CONTROL_CAL);



		/* Poll for offset calibration complete */

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah),

				   AR_PHY_AGC_CONTROL_CAL,

				   0, AH_WAIT_TIMEOUT)) {

			ath_dbg(common, CALIBRATE,
@@ -880,7 +880,7 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
			if (!AR_SREV_9287_11_OR_LATER(ah))

				REG_SET_BIT(ah, AR_PHY_ADC_CTL,

					    AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

			REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),

				    AR_PHY_AGC_CONTROL_FLTR_CAL);

		}

	}

drivers/net/wireless/ath/ath9k/ar9002_hw.c

+5 −5
Original line number Diff line number Diff line
@@ -249,9 +249,9 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 


	if (power_off) {

		/* clear bit 19 to disable L1 */

		REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

		REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);



		val = REG_READ(ah, AR_WA);

		val = REG_READ(ah, AR_WA(ah));



		/*

		 * Set PCIe workaround bits
@@ -286,7 +286,7 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 
		if (AR_SREV_9285E_20(ah))

			val |= AR_WA_BIT23;



		REG_WRITE(ah, AR_WA, val);

		REG_WRITE(ah, AR_WA(ah), val);

	} else {

		if (ah->config.pcie_waen) {

			val = ah->config.pcie_waen;
@@ -314,10 +314,10 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 
		if (AR_SREV_9285E_20(ah))

			val |= AR_WA_BIT23;



		REG_WRITE(ah, AR_WA, val);

		REG_WRITE(ah, AR_WA(ah), val);



		/* set bit 19 to allow forcing of pcie core into L1 state */

		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

		REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);

	}

}

drivers/net/wireless/ath/ath9k/ar9002_mac.c

+7 −7
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 


static void ar9002_hw_rx_enable(struct ath_hw *ah)

{

	REG_WRITE(ah, AR_CR, AR_CR_RXE);

	REG_WRITE(ah, AR_CR, AR_CR_RXE(ah));

}



static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
@@ -40,14 +40,14 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked, 
	struct ath_common *common = ath9k_hw_common(ah);



	if (!AR_SREV_9100(ah)) {

		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {

			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)

		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE(ah)) & AR_INTR_MAC_IRQ) {

			if ((REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah))

			    == AR_RTC_STATUS_ON) {

				isr = REG_READ(ah, AR_ISR);

			}

		}



		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &

		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah)) &

			AR_INTR_SYNC_DEFAULT;



		*masked = 0;
@@ -138,7 +138,7 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked, 
		u32 s5_s;



		if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {

			s5_s = REG_READ(ah, AR_ISR_S5_S);

			s5_s = REG_READ(ah, AR_ISR_S5_S(ah));

		} else {

			s5_s = REG_READ(ah, AR_ISR_S5);

		}
@@ -201,8 +201,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked, 
				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");

		}



		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);

		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR(ah), sync_cause);

		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR(ah));

	}



	return true;

drivers/net/wireless/ath/ath9k/ar9002_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -281,10 +281,10 @@ static void ar9002_olc_init(struct ath_hw *ah) 
{

	u32 i;



	if (!OLC_FOR_AR9280_20_LATER)

	if (!OLC_FOR_AR9280_20_LATER(ah))

		return;



	if (OLC_FOR_AR9287_10_LATER) {

	if (OLC_FOR_AR9287_10_LATER(ah)) {

		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,

				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);

		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,