Unverified Commit b41ae495 authored by Sarah Walker's avatar Sarah Walker Committed by Maxime Ripard
Browse files

drm/imagination: Add GPU register headers 



Changes since v8:
- Corrected license identifiers

Changes since v5:
- Split up header commit due to size

Signed-off-by: default avatarSarah Walker <sarah.walker@imgtec.com>
Signed-off-by: default avatarDonald Robson <donald.robson@imgtec.com>
Reviewed-by: default avatarMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/9f1fbf6c18e9644ac10712e05893701f06aee6ae.1700668843.git.donald.robson@imgtec.com


Signed-off-by: default avatarMaxime Ripard <mripard@kernel.org>
parent 1f88f017

drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h

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File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/imagination/pvr_rogue_cr_defs_client.h

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */

/* Copyright (c) 2023 Imagination Technologies Ltd. */



#ifndef PVR_ROGUE_CR_DEFS_CLIENT_H

#define PVR_ROGUE_CR_DEFS_CLIENT_H



/* clang-format off */



/*

 * This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is

 * provided in both X & Y axis.

 * This register needs to be set based on the ISP Samples Per Pixel a core supports.

 *

 * When ISP Samples Per Pixel = 1:

 * 2xmsaa is achieved by enabling Y - TE does AA on Y plane only

 * 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane

 * 8xmsaa not supported by XE cores

 *

 * When ISP Samples Per Pixel = 2:

 * 2xmsaa is achieved by enabling X2 - does not affect TE

 * 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only

 * 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane

 * 8xmsaa not supported by XE cores

 *

 * When ISP Samples Per Pixel = 4:

 * 2xmsaa is achieved by enabling X2 - does not affect TE

 * 4xmsaa is achieved by enabling Y2 and X2 - TE does AA on Y plane only

 * 8xmsaa not supported by XE cores

 */

/* Register ROGUE_CR_TE_AA */

#define ROGUE_CR_TE_AA 0x0C00U

#define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full

/* Y2

 * Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within

 * TPW.

 */

#define ROGUE_CR_TE_AA_Y2_SHIFT 3

#define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF7

#define ROGUE_CR_TE_AA_Y2_EN 0x00000008

/* Y

 * Anti-Aliasing in Y Plane Enabled

 */

#define ROGUE_CR_TE_AA_Y_SHIFT 2

#define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB

#define ROGUE_CR_TE_AA_Y_EN 0x00000004

/* X

 * Anti-Aliasing in X Plane Enabled

 */

#define ROGUE_CR_TE_AA_X_SHIFT 1

#define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD

#define ROGUE_CR_TE_AA_X_EN 0x00000002

/* X2

 * 2x Anti-Aliasing Enabled, affects PPP only

 */

#define ROGUE_CR_TE_AA_X2_SHIFT                             (0U)

#define ROGUE_CR_TE_AA_X2_CLRMSK                            (0xFFFFFFFEU)

#define ROGUE_CR_TE_AA_X2_EN                                (0x00000001U)



/* MacroTile Boundaries X Plane */

/* Register ROGUE_CR_TE_MTILE1 */

#define ROGUE_CR_TE_MTILE1 0x0C08

#define ROGUE_CR_TE_MTILE1_MASKFULL 0x0000000007FFFFFFull

/* X1 default: 0x00000004

 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across

 * tile

 */

#define ROGUE_CR_TE_MTILE1_X1_SHIFT 18

#define ROGUE_CR_TE_MTILE1_X1_CLRMSK 0xF803FFFF

/* X2 default: 0x00000008

 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile

 */

#define ROGUE_CR_TE_MTILE1_X2_SHIFT 9U

#define ROGUE_CR_TE_MTILE1_X2_CLRMSK 0xFFFC01FF

/* X3 default: 0x0000000c

 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile

 */

#define ROGUE_CR_TE_MTILE1_X3_SHIFT 0

#define ROGUE_CR_TE_MTILE1_X3_CLRMSK 0xFFFFFE00



/* MacroTile Boundaries Y Plane. */

/* Register ROGUE_CR_TE_MTILE2 */

#define ROGUE_CR_TE_MTILE2 0x0C10

#define ROGUE_CR_TE_MTILE2_MASKFULL 0x0000000007FFFFFFull

/* Y1 default: 0x00000004

 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile

 * height

 */

#define ROGUE_CR_TE_MTILE2_Y1_SHIFT 18

#define ROGUE_CR_TE_MTILE2_Y1_CLRMSK 0xF803FFFF

/* Y2 default: 0x00000008

 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height

 */

#define ROGUE_CR_TE_MTILE2_Y2_SHIFT 9

#define ROGUE_CR_TE_MTILE2_Y2_CLRMSK 0xFFFC01FF

/* Y3 default: 0x0000000c

 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height

 */

#define ROGUE_CR_TE_MTILE2_Y3_SHIFT 0

#define ROGUE_CR_TE_MTILE2_Y3_CLRMSK 0xFFFFFE00



/*

 * In order to perform the tiling operation and generate the display list the maximum screen size

 * must be configured in terms of the number of tiles in X & Y axis.

 */



/* Register ROGUE_CR_TE_SCREEN */

#define ROGUE_CR_TE_SCREEN 0x0C18U

#define ROGUE_CR_TE_SCREEN_MASKFULL 0x00000000001FF1FFull

/* YMAX default: 0x00000010

 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size

 */

#define ROGUE_CR_TE_SCREEN_YMAX_SHIFT 12

#define ROGUE_CR_TE_SCREEN_YMAX_CLRMSK 0xFFE00FFF

/* XMAX default: 0x00000010

 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size

 */

#define ROGUE_CR_TE_SCREEN_XMAX_SHIFT 0

#define ROGUE_CR_TE_SCREEN_XMAX_CLRMSK 0xFFFFFE00



/*

 * In order to perform the tiling operation and generate the display list the maximum screen size

 * must be configured in terms of the number of pixels in X & Y axis since this may not be the same

 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.

 */

/* Register ROGUE_CR_PPP_SCREEN */

#define ROGUE_CR_PPP_SCREEN 0x0C98

#define ROGUE_CR_PPP_SCREEN_MASKFULL 0x000000007FFF7FFFull

/* PIXYMAX

 * Screen height in pixels. (16K x 16K max screen size)

 */

#define ROGUE_CR_PPP_SCREEN_PIXYMAX_SHIFT 16

#define ROGUE_CR_PPP_SCREEN_PIXYMAX_CLRMSK 0x8000FFFF

/* PIXXMAX

 * Screen width in pixels.(16K x 16K max screen size)

 */

#define ROGUE_CR_PPP_SCREEN_PIXXMAX_SHIFT 0

#define ROGUE_CR_PPP_SCREEN_PIXXMAX_CLRMSK 0xFFFF8000



/* Register ROGUE_CR_ISP_MTILE_SIZE */

#define ROGUE_CR_ISP_MTILE_SIZE 0x0F18

#define ROGUE_CR_ISP_MTILE_SIZE_MASKFULL 0x0000000003FF03FFull

/* X

 * Macrotile width, in tiles. A value of zero corresponds to the maximum size

 */

#define ROGUE_CR_ISP_MTILE_SIZE_X_SHIFT 16

#define ROGUE_CR_ISP_MTILE_SIZE_X_CLRMSK 0xFC00FFFF

#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSHIFT 0

#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSIZE 1

/* Y

 * Macrotile height, in tiles. A value of zero corresponds to the maximum size

 */

#define ROGUE_CR_ISP_MTILE_SIZE_Y_SHIFT 0

#define ROGUE_CR_ISP_MTILE_SIZE_Y_CLRMSK 0xFFFFFC00

#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSHIFT 0

#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSIZE 1



/* clang-format on */



#endif /* PVR_ROGUE_CR_DEFS_CLIENT_H */

drivers/gpu/drm/imagination/pvr_rogue_defs.h

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */

/* Copyright (c) 2023 Imagination Technologies Ltd. */



#ifndef PVR_ROGUE_DEFS_H

#define PVR_ROGUE_DEFS_H



#include "pvr_rogue_cr_defs.h"



#include <linux/bits.h>



/*

 ******************************************************************************

 * ROGUE Defines

 ******************************************************************************

 */



#define ROGUE_FW_MAX_NUM_OS (8U)

#define ROGUE_FW_HOST_OS (0U)

#define ROGUE_FW_GUEST_OSID_START (1U)



#define ROGUE_FW_THREAD_0 (0U)

#define ROGUE_FW_THREAD_1 (1U)



#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((s32)(x)) > 0) ? ((x) / 8) : (0))



#define MAX_HW_GEOM_FRAG_CONTEXTS 2U



#define ROGUE_CR_CLK_CTRL_ALL_ON \

	(0x5555555555555555ull & ROGUE_CR_CLK_CTRL_MASKFULL)

#define ROGUE_CR_CLK_CTRL_ALL_AUTO \

	(0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL_MASKFULL)

#define ROGUE_CR_CLK_CTRL2_ALL_ON \

	(0x5555555555555555ull & ROGUE_CR_CLK_CTRL2_MASKFULL)

#define ROGUE_CR_CLK_CTRL2_ALL_AUTO \

	(0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL2_MASKFULL)



#define ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN    \

	(ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN)



/* SOFT_RESET Rascal and DUSTs bits */

#define ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN    \

	(ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN | \

	 ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN)



/* SOFT_RESET steps as defined in the TRM */

#define ROGUE_S7_SOFT_RESET_DUSTS (ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN)



#define ROGUE_S7_SOFT_RESET_JONES                                 \

	(ROGUE_CR_SOFT_RESET_PM_EN | ROGUE_CR_SOFT_RESET_VDM_EN | \

	 ROGUE_CR_SOFT_RESET_ISP_EN)



#define ROGUE_S7_SOFT_RESET_JONES_ALL                             \

	(ROGUE_S7_SOFT_RESET_JONES | ROGUE_CR_SOFT_RESET_BIF_EN | \

	 ROGUE_CR_SOFT_RESET_SLC_EN | ROGUE_CR_SOFT_RESET_GARTEN_EN)



#define ROGUE_S7_SOFT_RESET2                                                  \

	(ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN | ROGUE_CR_SOFT_RESET2_PIXEL_EN | \

	 ROGUE_CR_SOFT_RESET2_CDM_EN | ROGUE_CR_SOFT_RESET2_VERTEX_EN)



#define ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT (12U)

#define ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE \

	BIT(ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT)



#define ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT (14U)

#define ROGUE_BIF_PM_VIRTUAL_PAGE_SIZE BIT(ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT)



#define ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE (16U)



/*

 * To get the number of required Dusts, divide the number of

 * clusters by 2 and round up

 */

#define ROGUE_REQ_NUM_DUSTS(CLUSTERS) (((CLUSTERS) + 1U) / 2U)



/*

 * To get the number of required Bernado/Phantom(s), divide

 * the number of clusters by 4 and round up

 */

#define ROGUE_REQ_NUM_PHANTOMS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)

#define ROGUE_REQ_NUM_BERNADOS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)

#define ROGUE_REQ_NUM_BLACKPEARLS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)



/*

 * FW MMU contexts

 */

#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */

#define MMU_CONTEXT_MAPPING_FWIF (0x0) /* Host/FW data */



/*

 * Utility macros to calculate CAT_BASE register addresses

 */

#define BIF_CAT_BASEX(n)          \

	(ROGUE_CR_BIF_CAT_BASE0 + \

	 (n) * (ROGUE_CR_BIF_CAT_BASE1 - ROGUE_CR_BIF_CAT_BASE0))



#define FWCORE_MEM_CAT_BASEX(n)                 \

	(ROGUE_CR_FWCORE_MEM_CAT_BASE0 +        \

	 (n) * (ROGUE_CR_FWCORE_MEM_CAT_BASE1 - \

		ROGUE_CR_FWCORE_MEM_CAT_BASE0))



/*

 * FWCORE wrapper register defines

 */

#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT \

	ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT

#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_CLRMSK \

	ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK

#define FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT (12U)



#define ROGUE_MAX_COMPUTE_SHARED_REGISTERS (2 * 1024)

#define ROGUE_MAX_VERTEX_SHARED_REGISTERS 1024

#define ROGUE_MAX_PIXEL_SHARED_REGISTERS 1024

#define ROGUE_CSRM_LINE_SIZE_IN_DWORDS (64 * 4 * 4)



#define ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE 64

#define ROGUE_CDMCTRL_USC_COMMON_SIZE_UPPER 256



/*

 * The maximum amount of local memory which can be allocated by a single kernel

 * (in dwords/32-bit registers).

 *

 * ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE is in bytes so we divide by four.

 */

#define ROGUE_MAX_PER_KERNEL_LOCAL_MEM_SIZE_REGS ((ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE * \

						   ROGUE_CDMCTRL_USC_COMMON_SIZE_UPPER) >> 2)



/*

 ******************************************************************************

 * WA HWBRNs

 ******************************************************************************

 */



/* GPU CR timer tick in GPU cycles */

#define ROGUE_CRTIME_TICK_IN_CYCLES (256U)



/* for nohw multicore return max cores possible to client */

#define ROGUE_MULTICORE_MAX_NOHW_CORES (4U)



/*

 * If the size of the SLC is less than this value then the TPU bypasses the SLC.

 */

#define ROGUE_TPU_CACHED_SLC_SIZE_THRESHOLD (128U * 1024U)



/*

 * If the size of the SLC is bigger than this value then the TCU must not be

 * bypassed in the SLC.

 * In XE_MEMORY_HIERARCHY cores, the TCU is bypassed by default.

 */

#define ROGUE_TCU_CACHED_SLC_SIZE_THRESHOLD (32U * 1024U)



/*

 * Register used by the FW to track the current boot stage (not used in MIPS)

 */

#define ROGUE_FW_BOOT_STAGE_REGISTER (ROGUE_CR_POWER_ESTIMATE_RESULT)



/*

 * Virtualisation definitions

 */

#define ROGUE_VIRTUALISATION_REG_SIZE_PER_OS \

	(ROGUE_CR_MTS_SCHEDULE1 - ROGUE_CR_MTS_SCHEDULE)



/*

 * Macro used to indicate which version of HWPerf is active

 */

#define ROGUE_FEATURE_HWPERF_ROGUE



/*

 * Maximum number of cores supported by TRP

 */

#define ROGUE_TRP_MAX_NUM_CORES (4U)



#endif /* PVR_ROGUE_DEFS_H */