Commit b4985cce authored by Radhakrishna Sripada's avatar Radhakrishna Sripada
Browse files

drm/i915/xelpg: Add Wa_14020495402 



Disable clockgating for TDL SVHS fub.

v2: Implement in general render/compute wa's(MattR)

Bspec: 46045
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240318210025.562698-1-radhakrishna.sripada@intel.com
parent 8d4ba9fc

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1215,6 +1215,7 @@ 
#define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)

#define   GEN12_ENABLE_LARGE_GRF_MODE		REG_BIT(12)

#define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)

#define   XELPG_DISABLE_TDL_SVHS_GATING		REG_BIT(1)

#define   GEN12_DISABLE_DOP_GATING              REG_BIT(0)



#define RT_CTRL					MCR_REG(0xe530)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −1
Original line number Diff line number Diff line
@@ -2891,10 +2891,14 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 


	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||

	    IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))

	    IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74))) {

		/* Wa_14017856879 */

		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);



		/* Wa_14020495402 */

		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING);

	}



	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))

		/*