Commit b5d712e5 authored by Shawn Lin's avatar Shawn Lin Committed by Manivannan Sadhasivam
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PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port 



Some Rockchip PCIe Root Ports report bogus size of 1GiB for the BAR
memories and they cause below resource allocation issue during probe.

  pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port
  pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x3fffffff]
  pci 0000:00:00.0: BAR 1 [mem 0x00000000-0x3fffffff]
  pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref]
	...
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign
  pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: assigned
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: releasing
  pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: releasing
  pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space
  pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign

Since there is no use of the Root Port BAR memories, disable both of them.

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
[mani: reworded the description and comment]
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/1766570461-138256-1-git-send-email-shawn.lin@rock-chips.com
parent 8f0b4cce

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+8 −0
Original line number Diff line number Diff line
@@ -80,6 +80,8 @@ 
#define  PCIE_LINKUP_MASK		GENMASK(17, 16)

#define  PCIE_LTSSM_STATUS_MASK		GENMASK(5, 0)



#define PCIE_TYPE0_HDR_DBI2_OFFSET      0x100000



struct rockchip_pcie {

	struct dw_pcie pci;

	void __iomem *apb_base;
@@ -292,6 +294,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) 
	if (irq < 0)

		return irq;



	pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;



	ret = rockchip_pcie_init_irq_domain(rockchip);

	if (ret < 0)

		dev_err(dev, "failed to init irq domain\n");
@@ -302,6 +306,10 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) 
	rockchip_pcie_configure_l1ss(pci);

	rockchip_pcie_enable_l0s(pci);



	/* Disable Root Ports BAR0 and BAR1 as they report bogus size */

	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);

	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);



	return 0;

}