Commit b84e1cd2 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Thomas Hellström
Browse files

drm/xe/dg1: Fix power gate sequence. 

sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

VLK: 16314, 4304

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381


Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241219235536.454270-1-rodrigo.vivi@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 2f12e9c0)
Signed-off-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
parent 9ab49815

drivers/gpu/drm/xe/xe_gt_idle.c

+6 −4
Original line number Diff line number Diff line
@@ -122,11 +122,13 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt) 
	if (!xe_gt_is_media_type(gt))

		gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;



	if (xe->info.platform != XE_DG1) {

		for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {

			if ((gt->info.engine_mask & BIT(i)))

				gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |

							     VDN_MFXVDENC_POWERGATE_ENABLE(j));

		}

	}



	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

	if (xe->info.skip_guc_pc) {