Unverified Commit b852574c authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
Browse files

ASoC: SOF: Intel: lnl: Correct rom_status_reg 



ACE2 architecture changed the place where the ROM updates the status code
from the shared SRAM window (and HFFLGP1QW0 in ACE1) to HFDSC register for
the status and HFDEC (HFDSC + 4) for the error code.

The rom_status_reg is not used on LNL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.

Add new header file for lnl specific register definitions.

Fixes: 64a63d99 ("ASoC: SOF: Intel: LNL: Add support for Lunarlake platform")
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarLiam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-4-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1f1b820d

sound/soc/sof/intel/lnl.c

+2 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "hda-ipc.h"

#include "../sof-audio.h"

#include "mtl.h"

#include "lnl.h"

#include <sound/hda-mlink.h>



/* LunarLake ops */
@@ -199,7 +200,7 @@ const struct sof_intel_dsp_desc lnl_chip_info = { 
	.ipc_ack = MTL_DSP_REG_HFIPCXIDA,

	.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,

	.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,

	.rom_status_reg = MTL_DSP_ROM_STS,

	.rom_status_reg = LNL_DSP_REG_HFDSC,

	.rom_init_timeout = 300,

	.ssp_count = MTL_SSP_COUNT,

	.d0i3_offset = MTL_HDA_VS_D0I3C,

sound/soc/sof/intel/lnl.h

0 → 100644
+15 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */

/*

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.

 *

 * Copyright(c) 2024 Intel Corporation. All rights reserved.

 */



#ifndef __SOF_INTEL_LNL_H

#define __SOF_INTEL_LNL_H



#define LNL_DSP_REG_HFDSC		0x160200 /* DSP core0 status */

#define LNL_DSP_REG_HFDEC		0x160204 /* DSP core0 error */



#endif /* __SOF_INTEL_LNL_H */