Commit b8ae9d34 authored by Paul Barker's avatar Paul Barker Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const 



The r9a07g043_mod_clks and r9a07g043_resets arrays describe the module
clocks and reset signals (respectively) in this SoC and do not change at
runtime.

Signed-off-by: default avatarPaul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240320082831.9666-1-paul.barker.ct@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c69fe2ae

drivers/clk/renesas/r9a07g043-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
#endif

};



static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {

static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {

#ifdef CONFIG_ARM64

	DEF_MOD("gic",		R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,

				0x514, 0),
@@ -282,7 +282,7 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 
				0x5ac, 0),

};



static struct rzg2l_reset r9a07g043_resets[] = {

static const struct rzg2l_reset r9a07g043_resets[] = {

#ifdef CONFIG_ARM64

	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),

	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),