Commit b91872c5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-fix-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine fixes from Vinod Koul:

 - tegra210 div_u64 divison and max page fixes

 - revert Qualcomm unavailable register workaround which is causing
   regression, fixes have been proposed but still gaps are present so
   revert this for now

* tag 'dmaengine-fix-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
  dmaengine: Revert "dmaengine: qcom: bam_dma: Avoid writing unavailable register"
  dmaengine: tegra210-adma: check for adma max page
  dmaengine: tegra210-adma: Use div_u64 for 64 bit division
parents a760b101 e521f516

drivers/dma/qcom/bam_dma.c

+8 −16
Original line number Diff line number Diff line
@@ -59,9 +59,6 @@ struct bam_desc_hw { 
#define DESC_FLAG_NWD BIT(12)

#define DESC_FLAG_CMD BIT(11)



#define BAM_NDP_REVISION_START	0x20

#define BAM_NDP_REVISION_END	0x27



struct bam_async_desc {

	struct virt_dma_desc vd;
@@ -401,7 +398,6 @@ struct bam_device { 


	/* dma start transaction tasklet */

	struct tasklet_struct task;

	u32 bam_revision;

};



/**
@@ -445,8 +441,6 @@ static void bam_reset(struct bam_device *bdev) 
	writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));



	/* set descriptor threshold, start with 4 bytes */

	if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,

		     BAM_NDP_REVISION_END))

	writel_relaxed(DEFAULT_CNT_THRSHLD,

			bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
@@ -1006,8 +1000,7 @@ static void bam_apply_new_config(struct bam_chan *bchan, 
			maxburst = bchan->slave.src_maxburst;

		else

			maxburst = bchan->slave.dst_maxburst;

		if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,

			     BAM_NDP_REVISION_END))



		writel_relaxed(maxburst,

			       bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));

	}
@@ -1199,11 +1192,10 @@ static int bam_init(struct bam_device *bdev) 
	u32 val;



	/* read revision and configuration information */

	if (!bdev->num_ees) {

		val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));

	if (!bdev->num_ees)

		bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;



	bdev->bam_revision = val & REVISION_MASK;

	}



	/* check that configured EE is within range */

	if (bdev->ee >= bdev->num_ees)

drivers/dma/tegra210-adma.c

+5 −0
Original line number Diff line number Diff line
@@ -83,7 +83,9 @@ struct tegra_adma; 
 * @nr_channels: Number of DMA channels available.

 * @ch_fifo_size_mask: Mask for FIFO size field.

 * @sreq_index_offset: Slave channel index offset.

 * @max_page: Maximum ADMA Channel Page.

 * @has_outstanding_reqs: If DMA channel can have outstanding requests.

 * @set_global_pg_config: Global page programming.

 */

struct tegra_adma_chip_data {

	unsigned int (*adma_get_burst_config)(unsigned int burst_size);
@@ -99,6 +101,7 @@ struct tegra_adma_chip_data { 
	unsigned int nr_channels;

	unsigned int ch_fifo_size_mask;

	unsigned int sreq_index_offset;

	unsigned int max_page;

	bool has_outstanding_reqs;

	void (*set_global_pg_config)(struct tegra_adma *tdma);

};
@@ -854,6 +857,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { 
	.nr_channels		= 22,

	.ch_fifo_size_mask	= 0xf,

	.sreq_index_offset	= 2,

	.max_page		= 0,

	.has_outstanding_reqs	= false,

	.set_global_pg_config	= NULL,

};
@@ -871,6 +875,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { 
	.nr_channels		= 32,

	.ch_fifo_size_mask	= 0x1f,

	.sreq_index_offset	= 4,

	.max_page		= 4,

	.has_outstanding_reqs	= true,

	.set_global_pg_config	= tegra186_adma_global_page_config,

};