Commit bbff27b5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'nios2_updates_for_v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux 

Pull nios2 updates fromDinh Nguyen:

 - Use strscpy() and simply setup_cpuinfo()

 - Remove conflicting mappings when flushing tlb entries

 - Force update_mmu_cache on spurious pagefaults

* tag 'nios2_updates_for_v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  nios2: Replace strcpy() with strscpy() and simplify setup_cpuinfo()
  nios2: do not introduce conflicting mappings when flushing tlb entries
  nios2: force update_mmu_cache on spurious tlb-permission--related pagefaults
parents 408aa674 aa264d95

arch/nios2/include/asm/pgtable.h

+16 −0
Original line number Diff line number Diff line
@@ -291,4 +291,20 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, 
#define update_mmu_cache(vma, addr, ptep) \

	update_mmu_cache_range(NULL, vma, addr, ptep, 1)



static inline int pte_same(pte_t pte_a, pte_t pte_b);



#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS

static inline int ptep_set_access_flags(struct vm_area_struct *vma,

					unsigned long address, pte_t *ptep,

					pte_t entry, int dirty)

{

	if (!pte_same(*ptep, entry))

		set_ptes(vma->vm_mm, address, ptep, entry, 1);

	/*

	 * update_mmu_cache will unconditionally execute, handling both

	 * the case that the PTE changed and the spurious fault case.

	 */

	return true;

}



#endif /* _ASM_NIOS2_PGTABLE_H */

arch/nios2/kernel/cpuinfo.c

+1 −4
Original line number Diff line number Diff line
@@ -46,10 +46,7 @@ void __init setup_cpuinfo(void) 
	cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency");



	str = of_get_property(cpu, "altr,implementation", &len);

	if (str)

		strscpy(cpuinfo.cpu_impl, str, sizeof(cpuinfo.cpu_impl));

	else

		strcpy(cpuinfo.cpu_impl, "<unknown>");

	strscpy(cpuinfo.cpu_impl, str ?: "<unknown>");



	cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div");

	cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul");

arch/nios2/mm/tlb.c

+11 −7
Original line number Diff line number Diff line
@@ -144,10 +144,11 @@ static void flush_tlb_one(unsigned long addr) 
		if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))

			continue;



		tlbmisc = RDCTL(CTL_TLBMISC);

		pr_debug("Flush entry by writing way=%dl pid=%ld\n",

			 way, (pid_misc >> TLBMISC_PID_SHIFT));

			 way, ((tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK));



		tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);

		tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT) | (tlbmisc & TLBMISC_PID);

		WRCTL(CTL_TLBMISC, tlbmisc);

		WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));

		WRCTL(CTL_TLBACC, 0);
@@ -237,7 +238,8 @@ void flush_tlb_pid(unsigned long mmu_pid) 
			if (pid != mmu_pid)

				continue;



			tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);

			tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT) |

				  (pid << TLBMISC_PID_SHIFT);

			WRCTL(CTL_TLBMISC, tlbmisc);

			WRCTL(CTL_TLBACC, 0);

		}
@@ -272,15 +274,17 @@ void flush_tlb_all(void) 
	/* remember pid/way until we return */

	get_misc_and_pid(&org_misc, &pid_misc);



	/* Start at way 0, way is auto-incremented after each TLBACC write */

	WRCTL(CTL_TLBMISC, TLBMISC_WE);



	/* Map each TLB entry to physcal address 0 with no-access and a

	   bad ptbase */

	for (line = 0; line < cpuinfo.tlb_num_lines; line++) {

		WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));

		for (way = 0; way < cpuinfo.tlb_num_ways; way++)

		for (way = 0; way < cpuinfo.tlb_num_ways; way++) {

			// Code such as replace_tlb_one_pid assumes that no duplicate entries exist

			// for a single address across ways, so also use way as a dummy PID

			WRCTL(CTL_TLBMISC, TLBMISC_WE | (way << TLBMISC_WAY_SHIFT) |

					   (way << TLBMISC_PID_SHIFT));

			WRCTL(CTL_TLBACC, 0);

		}



		addr += PAGE_SIZE;

	}