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dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
Document the Last Level Cache Controller on Glymur SoC Glymur LLCC has 12 base register regions and an additional AND, OR broadcast region, total 14 register regions Increase maxItems for reg and reg-names to allow 14 entries for Glymur Reviewed-by:Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by:
Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com Signed-off-by:
Bjorn Andersson <andersson@kernel.org>