Unverified Commit bd17863a authored Nov 12, 2024 by Basavaraj Natikar Committed by Ilpo Järvinen Nov 13, 2024

platform/x86/amd: amd_3d_vcache: Add sysfs ABI documentation



Add documentation for the amd_3d_vcache sysfs bus platform driver
interface so that userspace applications can use it to change mode
preferences, either frequency or cache.

Co-developed-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Armin Wolf <W_Armin@gmx.de>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20241112170307.3745777-3-Basavaraj.Natikar@amd.com


Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

parent 5a67c0d1

Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache

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Original line number	Diff line number	Diff line
		What: /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode
		Date: November 2024
		KernelVersion: 6.13
		Contact: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
		Description: (RW) AMD 3D V-Cache optimizer allows users to switch CPU core
		rankings dynamically.

		This file switches between these two modes:
		- "frequency" cores within the faster CCD are prioritized before
		those in the slower CCD.
		- "cache" cores within the larger L3 CCD are prioritized before
		those in the smaller L3 CCD.

MAINTAINERS

+1 −0

Original line number	Diff line number	Diff line
		@@ -978,6 +978,7 @@ M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
		R: Mario Limonciello <mario.limonciello@amd.com>
		L: platform-driver-x86@vger.kernel.org
		S: Supported
		F: Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
		F: drivers/platform/x86/amd/x3d_vcache.c

		AMD ADDRESS TRANSLATION LIBRARY (ATL)