Commit be20ccc1 authored by Sam Protsenko's avatar Sam Protsenko Committed by Krzysztof Kozlowski
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clk: samsung: Group CPU clock functions by chip 



clk-cpu.c is going to get messy as new chips support is added.
Restructure the code by pulling related functions and definitions
together, grouping those by their relation to a particular chip or other
categories, to simplify the code navigation.

No functional change.

Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-7-semen.protsenko@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent c9bc1f77

drivers/clk/samsung/clk-cpu.c

+61 −53
Original line number Diff line number Diff line
@@ -38,34 +38,6 @@ 
#include "clk.h"

#include "clk-cpu.h"



#define E4210_SRC_CPU		0x0

#define E4210_STAT_CPU		0x200

#define E4210_DIV_CPU0		0x300

#define E4210_DIV_CPU1		0x304

#define E4210_DIV_STAT_CPU0	0x400

#define E4210_DIV_STAT_CPU1	0x404



#define E5433_MUX_SEL2		0x008

#define E5433_MUX_STAT2		0x208

#define E5433_DIV_CPU0		0x400

#define E5433_DIV_CPU1		0x404

#define E5433_DIV_STAT_CPU0	0x500

#define E5433_DIV_STAT_CPU1	0x504



#define E4210_DIV0_RATIO0_MASK	GENMASK(2, 0)

#define E4210_DIV1_HPM_MASK	GENMASK(6, 4)

#define E4210_DIV1_COPY_MASK	GENMASK(2, 0)

#define E4210_MUX_HPM_MASK	BIT(20)

#define E4210_DIV0_ATB_SHIFT	16

#define E4210_DIV0_ATB_MASK	(DIV_MASK << E4210_DIV0_ATB_SHIFT)



/* Divider stabilization time, msec */

#define MAX_STAB_TIME		10

#define MAX_DIV			8

#define DIV_MASK		GENMASK(2, 0)

#define DIV_MASK_ALL		GENMASK(31, 0)

#define MUX_MASK		GENMASK(2, 0)



struct exynos_cpuclk;



typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
@@ -103,6 +75,15 @@ struct exynos_cpuclk { 
	exynos_rate_change_fn_t			post_rate_cb;

};



/* ---- Common code --------------------------------------------------------- */



/* Divider stabilization time, msec */

#define MAX_STAB_TIME		10

#define MAX_DIV			8

#define DIV_MASK		GENMASK(2, 0)

#define DIV_MASK_ALL		GENMASK(31, 0)

#define MUX_MASK		GENMASK(2, 0)



/*

 * Helper function to wait until divider(s) have stabilized after the divider

 * value has changed.
@@ -142,33 +123,21 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, 
	pr_err("%s: re-parenting mux timed-out\n", __func__);

}



/* common round rate callback usable for all types of CPU clocks */

static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,

				     unsigned long *prate)

{

	struct clk_hw *parent = clk_hw_get_parent(hw);

	*prate = clk_hw_round_rate(parent, drate);

	return *prate;

}

/* ---- Exynos 3/4/5 -------------------------------------------------------- */



/* common recalc rate callback usable for all types of CPU clocks */

static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,

					       unsigned long parent_rate)

{

	/*

	 * The CPU clock output (armclk) rate is the same as its parent

	 * rate. Although there exist certain dividers inside the CPU

	 * clock block that could be used to divide the parent clock,

	 * the driver does not make use of them currently, except during

	 * frequency transitions.

	 */

	return parent_rate;

}

#define E4210_SRC_CPU		0x0

#define E4210_STAT_CPU		0x200

#define E4210_DIV_CPU0		0x300

#define E4210_DIV_CPU1		0x304

#define E4210_DIV_STAT_CPU0	0x400

#define E4210_DIV_STAT_CPU1	0x404



static const struct clk_ops exynos_cpuclk_clk_ops = {

	.recalc_rate = exynos_cpuclk_recalc_rate,

	.round_rate = exynos_cpuclk_round_rate,

};

#define E4210_DIV0_RATIO0_MASK	GENMASK(2, 0)

#define E4210_DIV1_HPM_MASK	GENMASK(6, 4)

#define E4210_DIV1_COPY_MASK	GENMASK(2, 0)

#define E4210_MUX_HPM_MASK	BIT(20)

#define E4210_DIV0_ATB_SHIFT	16

#define E4210_DIV0_ATB_MASK	(DIV_MASK << E4210_DIV0_ATB_SHIFT)



/*

 * Helper function to set the 'safe' dividers for the CPU clock. The parameters
@@ -300,6 +269,15 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, 
	return 0;

}



/* ---- Exynos5433 ---------------------------------------------------------- */



#define E5433_MUX_SEL2		0x008

#define E5433_MUX_STAT2		0x208

#define E5433_DIV_CPU0		0x400

#define E5433_DIV_CPU1		0x404

#define E5433_DIV_STAT_CPU0	0x500

#define E5433_DIV_STAT_CPU1	0x504



/*

 * Helper function to set the 'safe' dividers for the CPU clock. The parameters

 * div and mask contain the divider value and the register bit mask of the
@@ -398,6 +376,36 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, 
	return 0;

}



/* -------------------------------------------------------------------------- */



/* Common round rate callback usable for all types of CPU clocks */

static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,

				     unsigned long *prate)

{

	struct clk_hw *parent = clk_hw_get_parent(hw);

	*prate = clk_hw_round_rate(parent, drate);

	return *prate;

}



/* Common recalc rate callback usable for all types of CPU clocks */

static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,

					       unsigned long parent_rate)

{

	/*

	 * The CPU clock output (armclk) rate is the same as its parent

	 * rate. Although there exist certain dividers inside the CPU

	 * clock block that could be used to divide the parent clock,

	 * the driver does not make use of them currently, except during

	 * frequency transitions.

	 */

	return parent_rate;

}



static const struct clk_ops exynos_cpuclk_clk_ops = {

	.recalc_rate = exynos_cpuclk_recalc_rate,

	.round_rate = exynos_cpuclk_round_rate,

};



/*

 * This notifier function is called for the pre-rate and post-rate change

 * notifications of the parent clock of cpuclk.