Commit be30c827 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: pass dev_priv explicitly to DSPCNTR 



Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPCNTR register macro.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d9434a718658d7dc6dba1e8a54f80cd1503d0b33.1716469091.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 2468c0dd

drivers/gpu/drm/i915/display/i9xx_plane.c

+5 −5
Original line number Diff line number Diff line
@@ -496,7 +496,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, 
	 * disabled. Try to make the plane enable atomic by writing

	 * the control register just before the surface register.

	 */

	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);

	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
@@ -539,7 +539,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, 
	 */

	dspcntr = i9xx_plane_ctl_crtc(crtc_state);



	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);

	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
@@ -561,7 +561,7 @@ g4x_primary_async_flip(struct intel_plane *plane, 
	if (async_flip)

		dspcntr |= DISP_ASYNC_FLIP;



	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);

	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),

			  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
@@ -685,7 +685,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 
	if (!wakeref)

		return false;



	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));

	val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));



	ret = val & DISP_ENABLE;
@@ -1012,7 +1012,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	fb->dev = dev;



	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));

	val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));



	if (DISPLAY_VER(dev_priv) >= 4) {

		if (val & DISP_TILED) {

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#define DSPADDR_VLV(dev_priv, plane)		_MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)



#define _DSPACNTR				0x70180

#define DSPCNTR(plane)				_MMIO_PIPE2(dev_priv, plane, _DSPACNTR)

#define DSPCNTR(dev_priv, plane)		_MMIO_PIPE2(dev_priv, plane, _DSPACNTR)

#define   DISP_ENABLE			REG_BIT(31)

#define   DISP_PIPE_GAMMA_ENABLE	REG_BIT(30)

#define   DISP_FORMAT_MASK		REG_GENMASK(29, 26)

drivers/gpu/drm/i915/display/intel_color.c

+1 −1
Original line number Diff line number Diff line
@@ -1038,7 +1038,7 @@ static void i9xx_get_config(struct intel_crtc_state *crtc_state) 
	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 tmp;



	tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));

	tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));



	if (tmp & DISP_PIPE_GAMMA_ENABLE)

		crtc_state->gamma_enable = true;

drivers/gpu/drm/i915/display/intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -8233,11 +8233,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
		    pipe_name(pipe));



	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);

		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);

		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);

		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK);

	drm_WARN_ON(&dev_priv->drm,

drivers/gpu/drm/i915/gvt/cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -1315,7 +1315,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 
	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);



	if (info->plane == PLANE_A) {

		info->ctrl_reg = DSPCNTR(info->pipe);

		info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);

		info->stride_reg = DSPSTRIDE(info->pipe);

		info->surf_reg = DSPSURF(info->pipe);

	} else if (info->plane == PLANE_B) {
@@ -1381,7 +1381,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;

	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);



	info->ctrl_reg = DSPCNTR(info->pipe);

	info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);

	info->stride_reg = DSPSTRIDE(info->pipe);

	info->surf_reg = DSPSURF(info->pipe);