Commit be462c97 authored by Lizhi Hou's avatar Lizhi Hou Committed by Jeff Hugo
Browse files

accel/amdxdna: Add hardware context 



The hardware can be shared among multiple user applications. The
hardware resources are allocated/freed based on the request from
user application via driver IOCTLs.

DRM_IOCTL_AMDXDNA_CREATE_HWCTX
Allocate tile columns and create a hardware context structure to track the
usage and status of the resources. A hardware context ID is returned for
XDNA command execution.

DRM_IOCTL_AMDXDNA_DESTROY_HWCTX
Release hardware context based on its ID. The tile columns belong to
this hardware context will be reclaimed.

DRM_IOCTL_AMDXDNA_CONFIG_HWCTX
Config hardware context. Bind the hardware context to the required
resources.

Co-developed-by: default avatarMin Ma <min.ma@amd.com>
Signed-off-by: default avatarMin Ma <min.ma@amd.com>
Reviewed-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: default avatarLizhi Hou <lizhi.hou@amd.com>
Signed-off-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241118172942.2014541-6-lizhi.hou@amd.com
parent c88d3325

drivers/accel/amdxdna/Makefile

+2 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only



amdxdna-y := \

	aie2_ctx.o \

	aie2_message.o \

	aie2_pci.o \

	aie2_psp.o \

	aie2_smu.o \

	aie2_solver.o \

	amdxdna_ctx.o \

	amdxdna_mailbox.o \

	amdxdna_mailbox_helper.o \

	amdxdna_pci_drv.o \

drivers/accel/amdxdna/aie2_ctx.c

0 → 100644
+186 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2024, Advanced Micro Devices, Inc.

 */



#include <drm/amdxdna_accel.h>

#include <drm/drm_device.h>

#include <drm/drm_print.h>

#include <linux/types.h>



#include "aie2_pci.h"

#include "aie2_solver.h"

#include "amdxdna_ctx.h"

#include "amdxdna_mailbox.h"

#include "amdxdna_pci_drv.h"



static int aie2_hwctx_col_list(struct amdxdna_hwctx *hwctx)

{

	struct amdxdna_dev *xdna = hwctx->client->xdna;

	struct amdxdna_dev_hdl *ndev;

	int start, end, first, last;

	u32 width = 1, entries = 0;

	int i;



	if (!hwctx->num_tiles) {

		XDNA_ERR(xdna, "Number of tiles is zero");

		return -EINVAL;

	}



	ndev = xdna->dev_handle;

	if (unlikely(!ndev->metadata.core.row_count)) {

		XDNA_WARN(xdna, "Core tile row count is zero");

		return -EINVAL;

	}



	hwctx->num_col = hwctx->num_tiles / ndev->metadata.core.row_count;

	if (!hwctx->num_col || hwctx->num_col > ndev->total_col) {

		XDNA_ERR(xdna, "Invalid num_col %d", hwctx->num_col);

		return -EINVAL;

	}



	if (ndev->priv->col_align == COL_ALIGN_NATURE)

		width = hwctx->num_col;



	/*

	 * In range [start, end], find out columns that is multiple of width.

	 *	'first' is the first column,

	 *	'last' is the last column,

	 *	'entries' is the total number of columns.

	 */

	start =  xdna->dev_info->first_col;

	end =  ndev->total_col - hwctx->num_col;

	if (start > 0 && end == 0) {

		XDNA_DBG(xdna, "Force start from col 0");

		start = 0;

	}

	first = start + (width - start % width) % width;

	last = end - end % width;

	if (last >= first)

		entries = (last - first) / width + 1;

	XDNA_DBG(xdna, "start %d end %d first %d last %d",

		 start, end, first, last);



	if (unlikely(!entries)) {

		XDNA_ERR(xdna, "Start %d end %d width %d",

			 start, end, width);

		return -EINVAL;

	}



	hwctx->col_list = kmalloc_array(entries, sizeof(*hwctx->col_list), GFP_KERNEL);

	if (!hwctx->col_list)

		return -ENOMEM;



	hwctx->col_list_len = entries;

	hwctx->col_list[0] = first;

	for (i = 1; i < entries; i++)

		hwctx->col_list[i] = hwctx->col_list[i - 1] + width;



	print_hex_dump_debug("col_list: ", DUMP_PREFIX_OFFSET, 16, 4, hwctx->col_list,

			     entries * sizeof(*hwctx->col_list), false);

	return 0;

}



static int aie2_alloc_resource(struct amdxdna_hwctx *hwctx)

{

	struct amdxdna_dev *xdna = hwctx->client->xdna;

	struct alloc_requests *xrs_req;

	int ret;



	xrs_req = kzalloc(sizeof(*xrs_req), GFP_KERNEL);

	if (!xrs_req)

		return -ENOMEM;



	xrs_req->cdo.start_cols = hwctx->col_list;

	xrs_req->cdo.cols_len = hwctx->col_list_len;

	xrs_req->cdo.ncols = hwctx->num_col;

	xrs_req->cdo.qos_cap.opc = hwctx->max_opc;



	xrs_req->rqos.gops = hwctx->qos.gops;

	xrs_req->rqos.fps = hwctx->qos.fps;

	xrs_req->rqos.dma_bw = hwctx->qos.dma_bandwidth;

	xrs_req->rqos.latency = hwctx->qos.latency;

	xrs_req->rqos.exec_time = hwctx->qos.frame_exec_time;

	xrs_req->rqos.priority = hwctx->qos.priority;



	xrs_req->rid = (uintptr_t)hwctx;



	ret = xrs_allocate_resource(xdna->xrs_hdl, xrs_req, hwctx);

	if (ret)

		XDNA_ERR(xdna, "Allocate AIE resource failed, ret %d", ret);



	kfree(xrs_req);

	return ret;

}



static void aie2_release_resource(struct amdxdna_hwctx *hwctx)

{

	struct amdxdna_dev *xdna = hwctx->client->xdna;

	int ret;



	ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx);

	if (ret)

		XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret);

}



int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)

{

	struct amdxdna_client *client = hwctx->client;

	struct amdxdna_dev *xdna = client->xdna;

	struct amdxdna_hwctx_priv *priv;

	int ret;



	priv = kzalloc(sizeof(*hwctx->priv), GFP_KERNEL);

	if (!priv)

		return -ENOMEM;

	hwctx->priv = priv;



	ret = aie2_hwctx_col_list(hwctx);

	if (ret) {

		XDNA_ERR(xdna, "Create col list failed, ret %d", ret);

		goto free_priv;

	}



	ret = aie2_alloc_resource(hwctx);

	if (ret) {

		XDNA_ERR(xdna, "Alloc hw resource failed, ret %d", ret);

		goto free_col_list;

	}



	hwctx->status = HWCTX_STAT_INIT;



	XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);



	return 0;



free_col_list:

	kfree(hwctx->col_list);

free_priv:

	kfree(priv);

	return ret;

}



void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx)

{

	aie2_release_resource(hwctx);



	kfree(hwctx->col_list);

	kfree(hwctx->priv);

	kfree(hwctx->cus);

}



int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size)

{

	struct amdxdna_dev *xdna = hwctx->client->xdna;



	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));

	switch (type) {

	case DRM_AMDXDNA_HWCTX_CONFIG_CU:

	case DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF:

	case DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF:

		return -EOPNOTSUPP;

	default:

		XDNA_DBG(xdna, "Not supported type %d", type);

		return -EOPNOTSUPP;

	}

}

drivers/accel/amdxdna/aie2_message.c

+90 −0
Original line number Diff line number Diff line
@@ -3,13 +3,16 @@ 
 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

 */



#include <drm/amdxdna_accel.h>

#include <drm/drm_device.h>

#include <drm/drm_print.h>

#include <linux/errno.h>

#include <linux/pci.h>

#include <linux/types.h>



#include "aie2_msg_priv.h"

#include "aie2_pci.h"

#include "amdxdna_ctx.h"

#include "amdxdna_mailbox.h"

#include "amdxdna_mailbox_helper.h"

#include "amdxdna_pci_drv.h"
@@ -192,3 +195,90 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, 


	return 0;

}



int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)

{

	DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT);

	struct amdxdna_dev *xdna = ndev->xdna;

	struct xdna_mailbox_chann_res x2i;

	struct xdna_mailbox_chann_res i2x;

	struct cq_pair *cq_pair;

	u32 intr_reg;

	int ret;



	req.aie_type = 1;

	req.start_col = hwctx->start_col;

	req.num_col = hwctx->num_col;

	req.num_cq_pairs_requested = 1;

	req.pasid = hwctx->client->pasid;

	req.context_priority = 2;



	ret = aie2_send_mgmt_msg_wait(ndev, &msg);

	if (ret)

		return ret;



	hwctx->fw_ctx_id = resp.context_id;

	WARN_ONCE(hwctx->fw_ctx_id == -1, "Unexpected context id");



	cq_pair = &resp.cq_pair[0];

	x2i.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.head_addr);

	x2i.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.tail_addr);

	x2i.rb_start_addr   = AIE2_SRAM_OFF(ndev, cq_pair->x2i_q.buf_addr);

	x2i.rb_size	    = cq_pair->x2i_q.buf_size;



	i2x.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.head_addr);

	i2x.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.tail_addr);

	i2x.rb_start_addr   = AIE2_SRAM_OFF(ndev, cq_pair->i2x_q.buf_addr);

	i2x.rb_size	    = cq_pair->i2x_q.buf_size;



	ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id);

	if (ret == -EINVAL) {

		XDNA_ERR(xdna, "not able to create channel");

		goto out_destroy_context;

	}



	intr_reg = i2x.mb_head_ptr_reg + 4;

	hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x,

							      intr_reg, ret);

	if (!hwctx->priv->mbox_chann) {

		XDNA_ERR(xdna, "not able to create channel");

		ret = -EINVAL;

		goto out_destroy_context;

	}



	XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d",

		 hwctx->name, ret, resp.msix_id);

	XDNA_DBG(xdna, "%s created fw ctx %d pasid %d", hwctx->name,

		 hwctx->fw_ctx_id, hwctx->client->pasid);



	return 0;



out_destroy_context:

	aie2_destroy_context(ndev, hwctx);

	return ret;

}



int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)

{

	DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT);

	struct amdxdna_dev *xdna = ndev->xdna;

	int ret;



	if (hwctx->fw_ctx_id == -1)

		return 0;



	xdna_mailbox_stop_channel(hwctx->priv->mbox_chann);



	req.context_id = hwctx->fw_ctx_id;

	ret = aie2_send_mgmt_msg_wait(ndev, &msg);

	if (ret)

		XDNA_WARN(xdna, "%s destroy context failed, ret %d", hwctx->name, ret);



	xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann);

	XDNA_DBG(xdna, "%s destroyed fw ctx %d", hwctx->name,

		 hwctx->fw_ctx_id);

	hwctx->priv->mbox_chann = NULL;

	hwctx->fw_ctx_id = -1;



	return ret;

}

drivers/accel/amdxdna/aie2_pci.c

+43 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.

 */



#include <drm/amdxdna_accel.h>

#include <drm/drm_device.h>

#include <drm/drm_managed.h>

#include <drm/drm_print.h>
@@ -15,6 +16,7 @@ 
#include "aie2_msg_priv.h"

#include "aie2_pci.h"

#include "aie2_solver.h"

#include "amdxdna_ctx.h"

#include "amdxdna_mailbox.h"

#include "amdxdna_pci_drv.h"
@@ -210,6 +212,43 @@ static void aie2_mgmt_fw_fini(struct amdxdna_dev_hdl *ndev) 
	XDNA_DBG(ndev->xdna, "Firmware suspended");

}



static int aie2_xrs_load(void *cb_arg, struct xrs_action_load *action)

{

	struct amdxdna_hwctx *hwctx = cb_arg;

	struct amdxdna_dev *xdna;

	int ret;



	xdna = hwctx->client->xdna;



	hwctx->start_col = action->part.start_col;

	hwctx->num_col = action->part.ncols;

	ret = aie2_create_context(xdna->dev_handle, hwctx);

	if (ret)

		XDNA_ERR(xdna, "create context failed, ret %d", ret);



	return ret;

}



static int aie2_xrs_unload(void *cb_arg)

{

	struct amdxdna_hwctx *hwctx = cb_arg;

	struct amdxdna_dev *xdna;

	int ret;



	xdna = hwctx->client->xdna;



	ret = aie2_destroy_context(xdna->dev_handle, hwctx);

	if (ret)

		XDNA_ERR(xdna, "destroy context failed, ret %d", ret);



	return ret;

}



static struct xrs_action_ops aie2_xrs_actions = {

	.load = aie2_xrs_load,

	.unload = aie2_xrs_unload,

};



static void aie2_hw_stop(struct amdxdna_dev *xdna)

{

	struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
@@ -417,6 +456,7 @@ static int aie2_init(struct amdxdna_dev *xdna) 
	xrs_cfg.clk_list.cu_clk_list[2] = 1000;

	xrs_cfg.sys_eff_factor = 1;

	xrs_cfg.ddev = &xdna->ddev;

	xrs_cfg.actions = &aie2_xrs_actions;

	xrs_cfg.total_col = ndev->total_col;



	xdna->xrs_hdl = xrsm_init(&xrs_cfg);
@@ -453,4 +493,7 @@ static void aie2_fini(struct amdxdna_dev *xdna) 
const struct amdxdna_dev_ops aie2_ops = {

	.init           = aie2_init,

	.fini           = aie2_fini,

	.hwctx_init     = aie2_hwctx_init,

	.hwctx_fini     = aie2_hwctx_fini,

	.hwctx_config   = aie2_hwctx_config,

};

drivers/accel/amdxdna/aie2_pci.h

+13 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ enum psp_reg_idx { 
};



struct amdxdna_fw_ver;

struct amdxdna_hwctx;



struct psp_config {

	const void	*fw_buf;
@@ -117,6 +118,10 @@ struct rt_config { 
	u32	value;

};



struct amdxdna_hwctx_priv {

	void				*mbox_chann;

};



struct amdxdna_dev_hdl {

	struct amdxdna_dev		*xdna;

	const struct amdxdna_dev_priv	*priv;
@@ -189,4 +194,12 @@ int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *ver 
int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata);

int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,

				struct amdxdna_fw_ver *fw_ver);

int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);

int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);



/* aie2_hwctx.c */

int aie2_hwctx_init(struct amdxdna_hwctx *hwctx);

void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx);

int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);



#endif /* _AIE2_PCI_H_ */