Unverified Commit be5e8872 authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Palmer Dabbelt
Browse files

riscv: errata: Rename defines for Andes 



Use "ANDES" rather than "ANDESTECH" to unify the naming
convention with directory, file names, Kconfig options
and other definitions.

Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: default avatarCharles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-2-peterlin@andestech.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent f4cc33e7

arch/riscv/errata/andes/errata.c

+5 −5
Original line number Diff line number Diff line
@@ -18,9 +18,9 @@ 
#include <asm/sbi.h>

#include <asm/vendorid_list.h>



#define ANDESTECH_AX45MP_MARCHID	0x8000000000008a45UL

#define ANDESTECH_AX45MP_MIMPID		0x500UL

#define ANDESTECH_SBI_EXT_ANDES		0x0900031E

#define ANDES_AX45MP_MARCHID		0x8000000000008a45UL

#define ANDES_AX45MP_MIMPID		0x500UL

#define ANDES_SBI_EXT_ANDES		0x0900031E



#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void) 
	 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and

	 * cache is controllable only then CMO will be applied to the platform.

	 */

	ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,

	ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,

			0, 0, 0, 0, 0, 0);



	return ret.error ? 0 : ret.value;
@@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne 


	done = true;



	if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)

	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)

		return;



	if (!ax45mp_iocp_sw_workaround())

arch/riscv/include/asm/errata_list.h

+2 −2
Original line number Diff line number Diff line
@@ -12,8 +12,8 @@ 
#include <asm/vendorid_list.h>



#ifdef CONFIG_ERRATA_ANDES

#define ERRATA_ANDESTECH_NO_IOCP	0

#define ERRATA_ANDESTECH_NUMBER		1

#define ERRATA_ANDES_NO_IOCP 0

#define ERRATA_ANDES_NUMBER 1

#endif



#ifdef CONFIG_ERRATA_SIFIVE

arch/riscv/include/asm/vendorid_list.h

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
#ifndef ASM_VENDOR_LIST_H

#define ASM_VENDOR_LIST_H



#define ANDESTECH_VENDOR_ID	0x31e

#define ANDES_VENDOR_ID		0x31e

#define SIFIVE_VENDOR_ID	0x489

#define THEAD_VENDOR_ID		0x5b7

arch/riscv/kernel/alternative.c

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info 


	switch (cpu_mfr_info->vendor_id) {

#ifdef CONFIG_ERRATA_ANDES

	case ANDESTECH_VENDOR_ID:

	case ANDES_VENDOR_ID:

		cpu_mfr_info->patch_func = andes_errata_patch_func;

		break;

#endif