Commit bea98985 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use the correct mdclk/cdclk ratio in MBUS updates 



The current cdclk/mbus programming sequence is as follows:
1. intel_set_cdclk_pre_plane_update()
2. update_mbus_pre_enable()
3. intel_set_cdclk_post_plane_update()

when the actual mdclk/cdclk programming is postponed to
intel_set_cdclk_post_plane_update() we must keep using
the old mdclk/cdclk ratio during update_mbus_pre_enable().
This guarantees the programmed ratio matches the rest of
the hardware state (mdlk/cdclk/mbus joining).

v2: Extracted from the vblank synchronized mbus programming patch

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-12-ville.syrjala@linux.intel.com
parent 48b85304

drivers/gpu/drm/i915/display/intel_cdclk.c

+11 −0
Original line number Diff line number Diff line
@@ -2576,6 +2576,17 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 
			   update_cdclk, update_pipe_count);

}



bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)

{

	const struct intel_cdclk_state *old_cdclk_state =

		intel_atomic_get_old_cdclk_state(state);

	const struct intel_cdclk_state *new_cdclk_state =

		intel_atomic_get_new_cdclk_state(state);



	return new_cdclk_state && !new_cdclk_state->disable_pipes &&

		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;

}



/**

 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware

 * @state: intel atomic state

drivers/gpu/drm/i915/display/intel_cdclk.h

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 
			       const struct intel_cdclk_config *b);

u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,

			   const struct intel_cdclk_config *cdclk_config);

bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);

void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);

void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);

void intel_cdclk_dump_config(struct drm_i915_private *i915,

drivers/gpu/drm/i915/display/skl_watermark.c

+8 −11
Original line number Diff line number Diff line
@@ -3663,20 +3663,17 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state 
		intel_atomic_get_old_dbuf_state(state);

	const struct intel_dbuf_state *new_dbuf_state =

		intel_atomic_get_new_dbuf_state(state);

	int mdclk_cdclk_ratio;



	if (DISPLAY_VER(i915) >= 20 &&

	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {

		/*

		 * For Xe2LPD and beyond, when there is a change in the ratio

		 * between MDCLK and CDCLK, updates to related registers need to

		 * happen at a specific point in the CDCLK change sequence. In

		 * that case, we defer to the call to

		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.

		 */

		return;

	if (intel_cdclk_is_decreasing_later(state)) {

		/* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */

		mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio;

	} else {

		/* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */

		mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;

	}



	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,

	intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,

					    new_dbuf_state->joined_mbus);

}