Commit bf373e4c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Convert all remaining interrupt-controller bindings to DT schema

   - Convert Rockchip CDN-DP and Freescale TCON, M4IF, TigerP, LDB, PPC
     PMC, imx-drm, and ftm-quaddec to DT schema

   - Add bindings for fsl,vf610-pit, fsl,ls1021a-wdt, sgx,vz89te,
     maxim,max30208, ti,lp8864, and fairphone,fp5-sndcard

   - Add top-level constraints for renesas,vsp1 and renesas,fcp

   - Add missing constraint in amlogic,pinctrl-a4 'group' nodes

   - Adjust the allowed properties for dwc3-xilinx, sony,imx219,
     pci-iommu, and renesas,dsi

   - Add EcoNet vendor prefix

   - Fix the reserved-memory.yaml in fsl,qman-fqd

   - Drop obsolete numa.txt and cpu-topology.txt which are schemas in
     dtschema now

   - Drop Renesas RZ/N1S bindings

   - Ensure Arm cpu nodes don't allow undocumented properties. Add all
     the properties which are in use and undocumented. Drop the Mediatek
     cpufreq binding which is not a binding, but just what DT properties
     the driver uses.

   - Add compatibles for Renesas RZ/G3E and RZ/V2N Mali Bifrost GPU

   - Update documentation on defining child nodes with separate schemas

   - Add bindings to PSCI MAINTAINERS entry

  DT core:

   - Add new functions to simplify driver handling of 'memory-region'
     properties. Users to be added next cycle.

   - Simplify of_dma_set_restricted_buffer() to use
     of_for_each_phandle()

   - Add missing unlock on error in unittest_data_add()"

* tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (87 commits)
  dt-bindings: timer: Add fsl,vf610-pit.yaml
  dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC
  ASoC: dt-bindings: qcom,sm8250: Add Fairphone 5 sound card
  dt-bindings: arm/cpus: Allow 2 power-domains entries
  dt-bindings: usb: dwc3-xilinx: allow dma-coherent
  media: dt-bindings: sony,imx219: Allow props from video-interface-devices
  dt-bindings: soundwire: qcom: Document v2.1.0 version of IP block
  dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1021a-wdt
  dt-bindings: pinctrl: amlogic,pinctrl-a4: Add missing constraint on allowed 'group' node properties
  dt-bindings: display: rockchip: Convert cdn-dp-rockchip.txt to yaml
  dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller
  dt-bindings: trivial-devices: Add VZ89TE to trivial
  media: dt-bindings: renesas,vsp1: add top-level constraints
  media: dt-bindings: renesas,fcp: add top-level constraints
  dt-bindings: trivial-devices: Add Maxim max30208
  dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml reference
  dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schema
  dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schema
  dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schema
  dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schema
  ...
parents 8ca154e4 89ab97de

Documentation/devicetree/bindings/arm/cpus.yaml

+146 −88
Original line number Diff line number Diff line
@@ -10,9 +10,9 @@ maintainers: 
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>



description: |+

  The device tree allows to describe the layout of CPUs in a system through

  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")

  defining properties for every cpu.

  The device tree allows to describe the layout of CPUs in a system through the

  "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining

  properties for every cpu.



  Bindings for CPU nodes follow the Devicetree Specification, available from:
@@ -41,45 +41,40 @@ description: |+ 
properties:

  reg:

    maxItems: 1

    description: |

      Usage and definition depend on ARM architecture version and

      configuration:

    description: >

      Usage and definition depend on ARM architecture version and configuration:



      On uniprocessor ARM architectures previous to v7

      this property is required and must be set to 0.

      On uniprocessor ARM architectures previous to v7 this property is required

      and must be set to 0.



      On ARM 11 MPcore based systems this property is

        required and matches the CPUID[11:0] register bits.

      On ARM 11 MPcore based systems this property is required and matches the

      CPUID[11:0] register bits.



        Bits [11:0] in the reg cell must be set to

        bits [11:0] in CPU ID register.

        Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.



        All other bits in the reg cell must be set to 0.



      On 32-bit ARM v7 or later systems this property is

        required and matches the CPU MPIDR[23:0] register

        bits.

      On 32-bit ARM v7 or later systems this property is required and matches

      the CPU MPIDR[23:0] register bits.



        Bits [23:0] in the reg cell must be set to

        bits [23:0] in MPIDR.

        Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR.



        All other bits in the reg cell must be set to 0.



      On ARM v8 64-bit systems this property is required

        and matches the MPIDR_EL1 register affinity bits.

      On ARM v8 64-bit systems this property is required and matches the

      MPIDR_EL1 register affinity bits.



        * If cpus node's #address-cells property is set to 2



          The first reg cell bits [7:0] must be set to

          bits [39:32] of MPIDR_EL1.

          The first reg cell bits [7:0] must be set to bits [39:32] of

          MPIDR_EL1.



          The second reg cell bits [23:0] must be set to

          bits [23:0] of MPIDR_EL1.

          The second reg cell bits [23:0] must be set to bits [23:0] of

          MPIDR_EL1.



        * If cpus node's #address-cells property is set to 1



          The reg cell bits [23:0] must be set to bits [23:0]

          of MPIDR_EL1.

          The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1.



      All other bits in the reg cells must be set to 0.
@@ -273,103 +268,122 @@ properties: 
    description:

      The DT specification defines this as 64-bit always, but some 32-bit Arm

      systems have used a 32-bit value which must be supported.

      Required for systems that have an "enable-method"

        property value of "spin-table".



  cpu-idle-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      maxItems: 1

    description: |

      List of phandles to idle state nodes supported

      by this cpu (see ./idle-states.yaml).

    description:

      List of phandles to idle state nodes supported by this cpu (see

      ./idle-states.yaml).



  capacity-dmips-mhz:

    description:

      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in

      DMIPS/MHz, relative to highest capacity-dmips-mhz

      in the system.

      DMIPS/MHz, relative to highest capacity-dmips-mhz in the system.



  cci-control-port: true



  dynamic-power-coefficient:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      A u32 value that represents the running time dynamic

      power coefficient in units of uW/MHz/V^2. The

      coefficient can either be calculated from power

    description: >

      A u32 value that represents the running time dynamic power coefficient in

      units of uW/MHz/V^2. The coefficient can either be calculated from power

      measurements or derived by analysis.



      The dynamic power consumption of the CPU  is

      proportional to the square of the Voltage (V) and

      the clock frequency (f). The coefficient is used to

      The dynamic power consumption of the CPU  is proportional to the square of

      the Voltage (V) and the clock frequency (f). The coefficient is used to

      calculate the dynamic power as below -



      Pdyn = dynamic-power-coefficient * V^2 * f



      where voltage is in V, frequency is in MHz.



  interconnects:

    minItems: 1

    maxItems: 3



  nvmem-cells:

    maxItems: 1



  nvmem-cell-names:

    const: speed_grade



  performance-domains:

    maxItems: 1

    description:

      List of phandles and performance domain specifiers, as defined by

      bindings of the performance domain provider. See also

      dvfs/performance-domain.yaml.



  power-domains:

    description:

      List of phandles and PM domain specifiers, as defined by bindings of the

      PM domain provider (see also ../power_domain.txt).

    minItems: 1

    maxItems: 2



  power-domain-names:

    description:

      A list of power domain name strings sorted in the same order as the

      power-domains property.



      For PSCI based platforms, the name corresponding to the index of the PSCI

      PM domain provider, must be "psci". For SCMI based platforms, the name

      corresponding to the index of an SCMI performance domain provider, must be

      "perf".

    minItems: 1

    maxItems: 2

    items:

      enum: [ psci, perf, cpr ]



  qcom,saw:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      Specifies the SAW* node associated with this CPU.

  resets:

    maxItems: 1



      Required for systems that have an "enable-method" property

      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"

  arm-supply:

    deprecated: true

    description: Use 'cpu-supply' instead



      * arm/msm/qcom,saw2.txt

  cpu0-supply:

    deprecated: true

    description: Use 'cpu-supply' instead



  qcom,acc:

  mem-supply: true



  proc-supply:

    deprecated: true

    description: Use 'cpu-supply' instead



  sram-supply:

    deprecated: true

    description: Use 'mem-supply' instead



  mediatek,cci:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      Specifies the ACC* node associated with this CPU.

    description: Link to Mediatek Cache Coherent Interconnect



      Required for systems that have an "enable-method" property

      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or

      "qcom,msm8916-smp".

  qcom,saw:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Specifies the SAW node associated with this CPU.



      * arm/msm/qcom,kpss-acc.txt

  qcom,acc:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Specifies the ACC node associated with this CPU.



  qcom,freq-domain:

    description: Specifies the QCom CPUFREQ HW associated with the CPU.

    $ref: /schemas/types.yaml#/definitions/phandle-array

    maxItems: 1



  rockchip,pmu:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

    description: >

      Specifies the syscon node controlling the cpu core power domains.



      Optional for systems that have an "enable-method"

      property value of "rockchip,rk3066-smp"

      While optional, it is the preferred way to get access to

      the cpu-core power-domains.

      Optional for systems that have an "enable-method" property value of

      "rockchip,rk3066-smp". While optional, it is the preferred way to get

      access to the cpu-core power-domains.



  secondary-boot-reg:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

    description: >

      Required for systems that have an "enable-method" property value of

      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".



      This includes the following SoCs: |

      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550

      This includes the following SoCs:

      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550,

      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312



      The secondary-boot-reg property is a u32 value that specifies the
@@ -378,7 +392,13 @@ properties: 
      formed by encoding the target CPU id into the low bits of the

      physical start address it should jump to.



if:

  thermal-idle:

    type: object



allOf:

  - $ref: /schemas/cpu.yaml#

  - $ref: /schemas/opp/opp-v1.yaml#

  - if:

      # If the enable-method property contains one of those values

      properties:

        enable-method:
@@ -390,10 +410,48 @@ if: 
      # and if enable-method is present

      required:

        - enable-method



    then:

      required:

        - secondary-boot-reg

  - if:

      properties:

        enable-method:

          enum:

            - spin-table

            - renesas,r9a06g032-smp

      required:

        - enable-method

    then:

      required:

        - cpu-release-addr

  - if:

      properties:

        enable-method:

          enum:

            - qcom,kpss-acc-v1

            - qcom,kpss-acc-v2

            - qcom,msm8226-smp

            - qcom,msm8916-smp

      required:

        - enable-method

    then:

      required:

        - qcom,acc

        - qcom,saw

    else:

      if:

        # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use

        # "spin-table" or "psci" enable-methods. Disallowing the properties for

        # all other CPUs is the best we can do as there's not any way to

        # distinguish these Qualcomm platforms.

        not:

          properties:

            compatible:

              const: arm,cortex-a53

      then:

        properties:

          qcom,acc: false

          qcom,saw: false



required:

  - device_type
@@ -403,7 +461,7 @@ required: 
dependencies:

  rockchip,pmu: [enable-method]



additionalProperties: true

unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml

0 → 100644
+41 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module



description: collect the imx devices, which only have compatible and reg property



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    oneOf:

      - enum:

          - fsl,imx51-m4if

          - fsl,imx51-tigerp

          - fsl,imx51-aipstz

          - fsl,imx53-aipstz

          - fsl,imx7d-pcie-phy

      - items:

          - const: fsl,imx53-tigerp

          - const: fsl,imx51-tigerp



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    m4if@83fd8000 {

        compatible = "fsl,imx51-m4if";

        reg = <0x83fd8000 0x1000>;

    };

Documentation/devicetree/bindings/arm/freescale/m4if.txt

deleted100644 → 0
+0 −12
Original line number Diff line number Diff line 
* Freescale Multi Master Multi Memory Interface (M4IF) module



Required properties:

- compatible : Should be "fsl,imx51-m4if"

- reg : Address and length of the register set for the device



Example:



m4if: m4if@83fd8000 {

	compatible = "fsl,imx51-m4if";

	reg = <0x83fd8000 0x1000>;

};

Documentation/devicetree/bindings/arm/freescale/tigerp.txt

deleted100644 → 0
+0 −12
Original line number Diff line number Diff line 
* Freescale Tigerp platform module



Required properties:

- compatible : Should be "fsl,imx51-tigerp"

- reg : Address and length of the register set for the device



Example:



tigerp: tigerp@83fa0000 {

	compatible = "fsl,imx51-tigerp";

	reg = <0x83fa0000 0x28>;

};

Documentation/devicetree/bindings/arm/psci.yaml

+15 −15
Original line number Diff line number Diff line
@@ -191,27 +191,27 @@ examples: 
      #size-cells = <0>;

      #address-cells = <1>;



      CPU0: cpu@0 {

      cpu@0 {

        device_type = "cpu";

        compatible = "arm,cortex-a53";

        reg = <0x0>;

        enable-method = "psci";

        power-domains = <&CPU_PD0>;

        power-domains = <&cpu_pd0>;

        power-domain-names = "psci";

      };



      CPU1: cpu@1 {

      cpu@1 {

        device_type = "cpu";

        compatible = "arm,cortex-a53";

        reg = <0x100>;

        enable-method = "psci";

        power-domains = <&CPU_PD1>;

        power-domains = <&cpu_pd1>;

        power-domain-names = "psci";

      };



      idle-states {



        CPU_PWRDN: cpu-power-down {

        cpu_pwrdn: cpu-power-down {

          compatible = "arm,idle-state";

          arm,psci-suspend-param = <0x0000001>;

          entry-latency-us = <10>;
@@ -222,7 +222,7 @@ examples: 


      domain-idle-states {



        CLUSTER_RET: cluster-retention {

        cluster_ret: cluster-retention {

          compatible = "domain-idle-state";

          arm,psci-suspend-param = <0x1000011>;

          entry-latency-us = <500>;
@@ -230,7 +230,7 @@ examples: 
          min-residency-us = <2000>;

        };



        CLUSTER_PWRDN: cluster-power-down {

        cluster_pwrdn: cluster-power-down {

          compatible = "domain-idle-state";

          arm,psci-suspend-param = <0x1000031>;

          entry-latency-us = <2000>;
@@ -244,21 +244,21 @@ examples: 
      compatible = "arm,psci-1.0";

      method = "smc";



      CPU_PD0: power-domain-cpu0 {

      cpu_pd0: power-domain-cpu0 {

        #power-domain-cells = <0>;

        domain-idle-states = <&CPU_PWRDN>;

        power-domains = <&CLUSTER_PD>;

        domain-idle-states = <&cpu_pwrdn>;

        power-domains = <&cluster_pd>;

      };



      CPU_PD1: power-domain-cpu1 {

      cpu_pd1: power-domain-cpu1 {

        #power-domain-cells = <0>;

        domain-idle-states =  <&CPU_PWRDN>;

        power-domains = <&CLUSTER_PD>;

        domain-idle-states =  <&cpu_pwrdn>;

        power-domains = <&cluster_pd>;

      };



      CLUSTER_PD: power-domain-cluster {

      cluster_pd: power-domain-cluster {

        #power-domain-cells = <0>;

        domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;

        domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>;

      };

    };

...