Commit bf6daaa2 authored by Luca Ceresoli's avatar Luca Ceresoli Committed by Neil Armstrong
Browse files

drm/panel: simple: Add Tianma TM070JDHG34-00 panel support 

Add Tianma TM070JDHG34-00 7.0" 1280x800 LVDS RGB TFT LCD panel.

Panel info and datasheet: https://fortec.us/products/tm070jdhg34-00/



Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: default avatarLuca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://lore.kernel.org/r/20241216-tianma_tm070jdhg34-v2-2-0b319a0bac39@bootlin.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241216-tianma_tm070jdhg34-v2-2-0b319a0bac39@bootlin.com
parent 0c8d3b4a

drivers/gpu/drm/panel/panel-simple.c

+42 −0
Original line number Diff line number Diff line
@@ -4307,6 +4307,45 @@ static const struct panel_desc tianma_tm070jvhg33 = { 
	.bus_flags = DRM_BUS_FLAG_DE_HIGH,

};



/*

 * The datasheet computes total blanking as back porch + front porch, not

 * including sync pulse width. This is for both H and V. To make the total

 * blanking and period correct, subtract the pulse width from the front

 * porch.

 *

 * This works well for the Min and Typ values, but for Max values the sync

 * pulse width is higher than back porch + front porch, so work around that

 * by reducing the Max sync length value to 1 and then treating the Max

 * porches as in the Min and Typ cases.

 *

 * Exact datasheet values are added as a comment where they differ from the

 * ones implemented for the above reason.

 */

static const struct display_timing tianma_tm070jdhg34_00_timing = {

	.pixelclock = { 68400000, 71900000, 78100000 },

	.hactive = { 1280, 1280, 1280 },

	.hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */

	.hback_porch = { 5, 5, 5 },

	.hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */

	.vactive = { 800, 800, 800 },

	.vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */

	.vback_porch = { 2, 2, 2 },

	.vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */

	.flags = DISPLAY_FLAGS_DE_HIGH,

};



static const struct panel_desc tianma_tm070jdhg34_00 = {

	.timings = &tianma_tm070jdhg34_00_timing,

	.num_timings = 1,

	.bpc = 8,

	.size = {

		.width = 150, /* 149.76 */

		.height = 94, /* 93.60 */

	},

	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,

	.connector_type = DRM_MODE_CONNECTOR_LVDS,

};



static const struct display_timing tianma_tm070rvhg71_timing = {

	.pixelclock = { 27700000, 29200000, 39600000 },

	.hactive = { 800, 800, 800 },
@@ -5052,6 +5091,9 @@ static const struct of_device_id platform_of_match[] = { 
	}, {

		.compatible = "tianma,tm070jdhg30",

		.data = &tianma_tm070jdhg30,

	}, {

		.compatible = "tianma,tm070jdhg34-00",

		.data = &tianma_tm070jdhg34_00,

	}, {

		.compatible = "tianma,tm070jvhg33",

		.data = &tianma_tm070jvhg33,