Commit bfdb395a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_mtrr_for_v6.9_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 MTRR update from Borislav Petkov:

 - Relax the PAT MSR programming which was unnecessarily using the MTRR
   programming protocol of disabling the cache around the changes. The
   reason behind this is the current algorithm triggering a #VE
   exception for TDX guests and unnecessarily complicating things

* tag 'x86_mtrr_for_v6.9_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/pat: Simplify the PAT programming protocol
parents 742582ac ffc92cf3

arch/x86/kernel/cpu/cacheinfo.c

+4 −3
Original line number Diff line number Diff line
@@ -1118,15 +1118,16 @@ static void cache_cpu_init(void) 
	unsigned long flags;



	local_irq_save(flags);

	cache_disable();



	if (memory_caching_control & CACHE_MTRR)

	if (memory_caching_control & CACHE_MTRR) {

		cache_disable();

		mtrr_generic_set_state();

		cache_enable();

	}



	if (memory_caching_control & CACHE_PAT)

		pat_cpu_init();



	cache_enable();

	local_irq_restore(flags);

}

arch/x86/mm/pat/memtype.c

+3 −6
Original line number Diff line number Diff line
@@ -240,6 +240,8 @@ void pat_cpu_init(void) 
	}



	wrmsrl(MSR_IA32_CR_PAT, pat_msr_val);



	__flush_tlb_all();

}



/**
@@ -296,13 +298,8 @@ void __init pat_bp_init(void) 
	/*

	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are

	 * supported.

	 * When running as TDX guest setting the PAT MSR won't work either

	 * due to the requirement to set CR0.CD when doing so. Rely on

	 * firmware to have set the PAT MSR correctly.

	 */

	if (pat_disabled ||

	    cpu_feature_enabled(X86_FEATURE_XENPV) ||

	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {

	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {

		init_cache_modes(pat_msr_val);

		return;

	}