Commit c07b19de authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl 



Document Renesas RZ/V2L pinctrl bindings.  The RZ/V2L SoC is package-
and pin-compatible with RZ/G2L.  No driver changes are required as the
RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a
fallback.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220110134659.30424-7-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 96310a12

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+11 −4
Original line number Diff line number Diff line
@@ -4,14 +4,14 @@ 
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L combined Pin and GPIO controller

title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO

  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO

  controller.

  Pin multiplexing and GPIO configuration is performed on a per-pin basis.

  Each port features up to 8 pins, each of them configurable for GPIO function
@@ -20,9 +20,16 @@ description: 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}



      - items:

          - enum:

              - renesas,r9a07g054-pinctrl     # RZ/V2L

          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L



  reg:

    maxItems: 1