Commit c0f182c9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-drivers-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq controller updates from Thomas Gleixner:
 "Update for interrupt chip drivers:

   - Convert the generic interrupt chip to lock guards to remove copy &
     pasta boilerplate code and gotos.

   - A new driver fot the interrupt controller in the EcoNet EN751221
     MIPS SoC.

   - Extend the SG2042-MSI driver to support the new SG2044 SoC

   - Updates and cleanups for the (ancient) VT8500 driver

   - Improve the scalability of the ARM GICV4.1 ITS driver by utilizing
     node local copies a VM's interrupt translation table when possible.
     This results in a 12% reduction of VM IPI latency in certain
     workloads.

   - The usual cleanups and improvements all over the place"

* tag 'irq-drivers-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/irq-pruss-intc: Simplify chained interrupt handler setup
  irqchip/gic-v4.1: Use local 4_1 ITS to generate VSGI
  irqchip/econet-en751221: Switch to of_fwnode_handle()
  irqchip/irq-vt8500: Switch to irq_domain_create_*()
  irqchip/econet-en751221: Switch to irq_domain_create_linear()
  irqchip/irq-vt8500: Use fewer global variables and add error handling
  irqchip/irq-vt8500: Use a dedicated chained handler function
  irqchip/irq-vt8500: Don't require 8 interrupts from a chained controller
  irqchip/irq-vt8500: Drop redundant copy of the device node pointer
  irqchip/irq-vt8500: Split up ack/mask functions
  irqchip/sg2042-msi: Fix wrong type cast in sg2044_msi_irq_ack()
  irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller
  irqchip/sg2042-msi: Introduce configurable chipinfo for SG2042
  irqchip/sg2042-msi: Rename functions and data structures to be SG2042 agnostic
  dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller
  genirq/generic-chip: Fix incorrect lock guard conversions
  genirq/generic-chip: Remove unused lock wrappers
  irqchip: Convert generic irqchip locking to guards
  gpio: mvebu: Convert generic irqchip locking to guard()
  ARM: orion/gpio:: Convert generic irqchip locking to guard()
  ...
parents 60c1d948 3e402acd

Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml

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+78 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: EcoNet EN751221 Interrupt Controller



maintainers:

  - Caleb James DeLisle <cjd@cjdns.fr>



description:

  The EcoNet EN751221 Interrupt Controller is a simple interrupt controller

  designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can

  be routed to either VPE but not both, so to support per-CPU interrupts, a

  secondary IRQ number is allocated to control masking/unmasking on VPE#1. For

  lack of a better term we call these "shadow interrupts". The assignment of

  shadow interrupts is defined by the SoC integrator when wiring the interrupt

  lines, so they are configurable in the device tree.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    const: econet,en751221-intc



  reg:

    maxItems: 1



  "#interrupt-cells":

    const: 1



  interrupt-controller: true



  interrupts:

    maxItems: 1

    description: Interrupt line connecting this controller to its parent.



  econet,shadow-interrupts:

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    description:

      An array of interrupt number pairs where each pair represents a shadow

      interrupt relationship. The first number in each pair is the primary IRQ,

      and the second is its shadow IRQ used for VPE#1 control. For example,

      <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but

      when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.

    minItems: 1

    maxItems: 20

    items:

      items:

        - description: primary per-CPU IRQ

        - description: shadow IRQ number



required:

  - compatible

  - reg

  - interrupt-controller

  - "#interrupt-cells"

  - interrupts



additionalProperties: false



examples:

  - |

    interrupt-controller@1fb40000 {

        compatible = "econet,en751221-intc";

        reg = <0x1fb40000 0x100>;



        interrupt-controller;

        #interrupt-cells = <1>;



        interrupt-parent = <&cpuintc>;

        interrupts = <2>;



        econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;

    };

...

Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml

+3 −1
Original line number Diff line number Diff line
@@ -18,7 +18,9 @@ allOf: 


properties:

  compatible:

    const: sophgo,sg2042-msi

    enum:

      - sophgo,sg2042-msi

      - sophgo,sg2044-msi



  reg:

    items:

arch/arm/plat-orion/gpio.c

+2 −4
Original line number Diff line number Diff line
@@ -496,11 +496,10 @@ static void orion_gpio_unmask_irq(struct irq_data *d) 
	u32 reg_val;

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	reg_val = irq_reg_readl(gc, ct->regs.mask);

	reg_val |= mask;

	irq_reg_writel(gc, reg_val, ct->regs.mask);

	irq_gc_unlock(gc);

}



static void orion_gpio_mask_irq(struct irq_data *d)
@@ -510,11 +509,10 @@ static void orion_gpio_mask_irq(struct irq_data *d) 
	u32 mask = d->mask;

	u32 reg_val;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	reg_val = irq_reg_readl(gc, ct->regs.mask);

	reg_val &= ~mask;

	irq_reg_writel(gc, reg_val, ct->regs.mask);

	irq_gc_unlock(gc);

}



void __init orion_gpio_init(int gpio_base, int ngpio,

drivers/gpio/gpio-mvebu.c

+5 −10
Original line number Diff line number Diff line
@@ -408,9 +408,8 @@ static void mvebu_gpio_irq_ack(struct irq_data *d) 
	struct mvebu_gpio_chip *mvchip = gc->private;

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	mvebu_gpio_write_edge_cause(mvchip, ~mask);

	irq_gc_unlock(gc);

}



static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
@@ -420,10 +419,9 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	ct->mask_cache_priv &= ~mask;

	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);

	irq_gc_unlock(gc);

}



static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
@@ -433,11 +431,10 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	mvebu_gpio_write_edge_cause(mvchip, ~mask);

	ct->mask_cache_priv |= mask;

	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);

	irq_gc_unlock(gc);

}



static void mvebu_gpio_level_irq_mask(struct irq_data *d)
@@ -447,10 +444,9 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d) 
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	ct->mask_cache_priv &= ~mask;

	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);

	irq_gc_unlock(gc);

}



static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
@@ -460,10 +456,9 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	u32 mask = d->mask;



	irq_gc_lock(gc);

	guard(raw_spinlock)(&gc->lock);

	ct->mask_cache_priv |= mask;

	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);

	irq_gc_unlock(gc);

}



/*****************************************************************************

drivers/irqchip/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -166,6 +166,11 @@ config DW_APB_ICTL 
	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN_HIERARCHY



config ECONET_EN751221_INTC

	bool

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config FARADAY_FTINTC010

	bool

	select IRQ_DOMAIN