Commit c1380adf authored by Xianwei Zhao's avatar Xianwei Zhao Committed by Jerome Brunet
Browse files

clk: meson: s4: fix fixed_pll_dco clock 



The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.

Fixes: 57b55c76 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: default avatarXianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 1613e604

drivers/clk/meson/s4-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = { 
			.shift   = 0,

			.width   = 8,

		},

		.frac = {

			.reg_off = ANACTRL_FIXPLL_CTRL1,

			.shift   = 0,

			.width   = 17,

		},

		.n = {

			.reg_off = ANACTRL_FIXPLL_CTRL0,

			.shift   = 10,