Commit c158647c authored by Komal Bajaj's avatar Komal Bajaj Committed by Borislav Petkov (AMD)
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EDAC/qcom: Correct interrupt enable register configuration 



The previous implementation incorrectly configured the cmn_interrupt_2_enable
register for interrupt handling. Using cmn_interrupt_2_enable to configure
Tag, Data RAM ECC interrupts would lead to issues like double handling of the
interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
for interrupts which needs to be handled by EL3.

EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to configure
Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.

Fixes: 27450653 ("drivers: edac: Add EDAC driver support for QCOM SoCs")
Signed-off-by: default avatarKomal Bajaj <quic_kbajaj@quicinc.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/20241119064608.12326-1-quic_kbajaj@quicinc.com
parent a64dcfb4

drivers/edac/qcom_edac.c

+2 −2
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b 
	 * Configure interrupt enable registers such that Tag, Data RAM related

	 * interrupts are propagated to interrupt controller for servicing

	 */

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,

				 TRP0_INTERRUPT_ENABLE,

				 TRP0_INTERRUPT_ENABLE);

	if (ret)
@@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b 
	if (ret)

		return ret;



	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,

				 DRP0_INTERRUPT_ENABLE,

				 DRP0_INTERRUPT_ENABLE);

	if (ret)