Commit c18cee2e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/psr: Reintroduce HSW PSR1 registers 



Add back hsw'w special SRD/PSR1 registers.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
parent 6a6b0ab2

drivers/gpu/drm/i915/display/intel_psr.c

+16 −4
Original line number Diff line number Diff line
@@ -237,25 +237,37 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 
static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv,

			      enum transcoder cpu_transcoder)

{

	if (DISPLAY_VER(dev_priv) >= 8)

		return EDP_PSR_CTL(cpu_transcoder);

	else

		return HSW_SRD_CTL;

}



static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv,

				enum transcoder cpu_transcoder)

{

	if (DISPLAY_VER(dev_priv) >= 8)

		return EDP_PSR_DEBUG(cpu_transcoder);

	else

		return HSW_SRD_DEBUG;

}



static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv,

				   enum transcoder cpu_transcoder)

{

	if (DISPLAY_VER(dev_priv) >= 8)

		return EDP_PSR_PERF_CNT(cpu_transcoder);

	else

		return HSW_SRD_PERF_CNT;

}



static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv,

				 enum transcoder cpu_transcoder)

{

	if (DISPLAY_VER(dev_priv) >= 8)

		return EDP_PSR_STATUS(cpu_transcoder);

	else

		return HSW_SRD_STATUS;

}



static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_psr_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one

 * instance of it

 */

#define HSW_SRD_CTL				_MMIO(0x64800)

#define _SRD_CTL_A				0x60800

#define _SRD_CTL_EDP				0x6f800

#define EDP_PSR_CTL(tran)			_MMIO_TRANS2(tran, _SRD_CTL_A)
@@ -83,6 +84,7 @@ 
#define _SRD_AUX_DATA_EDP			0x6f814

#define EDP_PSR_AUX_DATA(tran, i)		_MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */



#define HSW_SRD_STATUS				_MMIO(0x64840)

#define _SRD_STATUS_A				0x60840

#define _SRD_STATUS_EDP				0x6f840

#define EDP_PSR_STATUS(tran)			_MMIO_TRANS2(tran, _SRD_STATUS_A)
@@ -107,12 +109,14 @@ 
#define   EDP_PSR_STATUS_SENDING_TP1		REG_BIT(4)

#define   EDP_PSR_STATUS_IDLE_MASK		REG_GENMASK(3, 0)



#define HSW_SRD_PERF_CNT		_MMIO(0x64844)

#define _SRD_PERF_CNT_A			0x60844

#define _SRD_PERF_CNT_EDP		0x6f844

#define EDP_PSR_PERF_CNT(tran)		_MMIO_TRANS2(tran, _SRD_PERF_CNT_A)

#define   EDP_PSR_PERF_CNT_MASK		REG_GENMASK(23, 0)



/* PSR_MASK on SKL+ */

#define HSW_SRD_DEBUG				_MMIO(0x64860)

#define _SRD_DEBUG_A				0x60860

#define _SRD_DEBUG_EDP				0x6f860

#define EDP_PSR_DEBUG(tran)			_MMIO_TRANS2(tran, _SRD_DEBUG_A)