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arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths
Add the OPP tables for each CPU clusters (cpu0-1, cpu2-3-4, cpu5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running HDK and QRD devices. The cpu2 and cpu5 tables are similar but must be kept separate to take in account that they define OPP for shared CPUs of two different clusters that can scale separately, thus vote different bandwidths. Signed-off-by:Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-3-a0c950540e68@linaro.org Signed-off-by:
Bjorn Andersson <andersson@kernel.org>