Commit c2e55b44 authored by Sai Pavan Boddu's avatar Sai Pavan Boddu Committed by Andi Shyti
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i2c: cadence: Avoid fifo clear after start 



The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bc ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: default avatarSai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: default avatarMichal Simek <michal.simek@amd.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@kernel.org>
parent dd5a440a

drivers/i2c/busses/i2c-cadence.c

+1 −0
Original line number Diff line number Diff line
@@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) 


	if (hold_clear) {

		ctrl_reg &= ~CDNS_I2C_CR_HOLD;

		ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;

		/*

		 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size

		 * register reaches '0'. This is an IP bug which causes transfer size