Commit c3ab84ef authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/xe: Expand XE_REG_OPTION_MASKED documentation 



Expand documentation and add an example to make clear this isn't about
generic masks in registers. Also, fix the doc regarding read operations:
the mask part has no effect on them.

Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231205155820.2133813-1-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 0f1d88f2

drivers/gpu/drm/xe/regs/xe_reg_defs.h

+10 −1
Original line number Diff line number Diff line
@@ -60,7 +60,16 @@ struct xe_reg_mcr { 


/**

 * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the

 * read/written bits on the lower 16 bits.

 * written bits on the lower 16 bits.

 *

 * It only applies to registers explicitly marked in bspec with

 * "Access: Masked". Registers with this option can have write operations to

 * specific lower bits by setting the corresponding upper bits. Other bits will

 * not be affected. This allows register writes without needing a RMW cycle and

 * without caching in software the register value.

 *

 * Example: a write with value 0x00010001 will set bit 0 and all other bits

 * retain their previous values.

 *

 * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()

 */