Commit c3d78c34 authored by Yicong Yang's avatar Yicong Yang Committed by Will Deacon
Browse files

perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores 



CPU_CYCLES is expected to count the logical CPU (PE) clock. Currently it's
preferred to use PMCCNTR_EL0 for counting CPU_CYCLES, but it'll count
processor clock rather than the PE clock (ARM DDI0487 L.b D13.1.3) if
one of the SMT siblings is not idle on a multi-threaded implementation.
So don't use it on SMT cores.

Introduce topology_core_has_smt() for knowing the SMT implementation and
cached it in arm_pmu::has_smt during allocation.

When counting cycles on SMT CPU 2-3 and CPU 3 is idle, without this
patch we'll get:
[root@client1 tmp]# perf stat -e cycles -A -C 2-3 -- stress-ng -c 1
--taskset 2 --timeout 1
[...]
 Performance counter stats for 'CPU(s) 2-3':

CPU2           2880457316      cycles
CPU3           2880459810      cycles
       1.254688470 seconds time elapsed

With this patch the idle state of CPU3 is observed as expected:
[root@client1 ~]#  perf stat -e cycles -A -C 2-3 -- stress-ng -c 1
--taskset 2 --timeout 1
[...]
 Performance counter stats for 'CPU(s) 2-3':

CPU2           2558580492      cycles
CPU3               305749      cycles
       1.113626410 seconds time elapsed

Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 3a866087

drivers/perf/arm_pmu.c

+6 −0
Original line number Diff line number Diff line
@@ -925,6 +925,12 @@ int armpmu_register(struct arm_pmu *pmu) 
	if (ret)

		return ret;



	/*

	 * By this stage we know our supported CPUs on either DT/ACPI platforms,

	 * detect the SMT implementation.

	 */

	pmu->has_smt = topology_core_has_smt(cpumask_first(&pmu->supported_cpus));



	if (!pmu->set_event_filter)

		pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;

drivers/perf/arm_pmuv3.c

+10 −0
Original line number Diff line number Diff line
@@ -981,6 +981,7 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, 
static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,

				     struct perf_event *event)

{

	struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);

	struct hw_perf_event *hwc = &event->hw;

	unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
@@ -1001,6 +1002,15 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc, 
	if (has_branch_stack(event))

		return false;



	/*

	 * The PMCCNTR_EL0 increments from the processor clock rather than

	 * the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue

	 * counting on a WFI PE if one of its SMT sibling is not idle on a

	 * multi-threaded implementation. So don't use it on SMT cores.

	 */

	if (cpu_pmu->has_smt)

		return false;



	return true;

}

include/linux/arch_topology.h

+11 −0
Original line number Diff line number Diff line
@@ -89,6 +89,17 @@ void remove_cpu_topology(unsigned int cpuid); 
void reset_cpu_topology(void);

int parse_acpi_topology(void);

void freq_inv_set_max_ratio(int cpu, u64 max_rate);



/*

 * Architectures like ARM64 don't have reliable architectural way to get SMT

 * information and depend on the firmware (ACPI/OF) report. Non-SMT core won't

 * initialize thread_id so we can use this to detect the SMT implementation.

 */

static inline bool topology_core_has_smt(int cpu)

{

	return cpu_topology[cpu].thread_id != -1;

}



#endif



#endif /* _LINUX_ARCH_TOPOLOGY_H_ */

include/linux/perf/arm_pmu.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ struct arm_pmu { 


	/* PMUv3 only */

	int		pmuver;

	bool		has_smt;

	u64		reg_pmmir;

	u64		reg_brbidr;

#define ARMV8_PMUV3_MAX_COMMON_EVENTS		0x40