Commit c5303240 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Keep TRANS_VBLANK.vblank_start==0 on ADL+ even when doing LRR updates 



intel_set_transcoder_timings() will set TRANS_VBLANK.vblank_start to 0
for clarity on ADL+ (non-DSI) because the hardware no longer uses that
value. Do the same in intel_set_transcoder_timings_lrr() to make sure
the registers stay consistent even when doing LRR timing updates.

Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250116201637.22486-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 8a2392fe

drivers/gpu/drm/i915/display/intel_display.c

+8 −0
Original line number Diff line number Diff line
@@ -2923,6 +2923,14 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc 
	crtc_vblank_start = adjusted_mode->crtc_vblank_start;

	crtc_vblank_end = adjusted_mode->crtc_vblank_end;



	if (DISPLAY_VER(dev_priv) >= 13) {

		/*

		 * VBLANK_START not used by hw, just clear it

		 * to make it stand out in register dumps.

		 */

		crtc_vblank_start = 1;

	}



	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);



	/*