Commit c5661431 authored by Unnathi Chalicheemala's avatar Unnathi Chalicheemala Committed by Bjorn Andersson
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arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block 



Chipsets before SM8450 have only one broadcast register (Broadcast_OR)
which is used to broadcast writes and check for status bit 0 only in
all channels.
>From SM8450 onwards, a new Broadcast_AND region was added which checks
for status bit 1. This hasn't been updated and Broadcast_OR region
was wrongly being used to check for status bit 1 all along.
Hence mapping Broadcast_AND region's address space to LLCC in SM8450.

Signed-off-by: default avatarUnnathi Chalicheemala <quic_uchalich@quicinc.com>
Link: https://lore.kernel.org/r/bfc817da4188abdf5b543bedafb9cb0eb82806c2.1717014052.git.quic_uchalich@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 809c20b1

arch/arm64/boot/dts/qcom/sm8450.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -4461,9 +4461,10 @@ system-cache-controller@19200000 { 
			compatible = "qcom,sm8450-llcc";

			reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,

			      <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,

			      <0 0x19a00000 0 0x80000>;

			      <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;

			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",

				    "llcc3_base", "llcc_broadcast_base";

				    "llcc3_base", "llcc_broadcast_base",

				    "llcc_broadcast_and_base";

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

		};