Commit c6005d4d authored by Joshua Yeong's avatar Joshua Yeong Committed by Conor Dooley
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dt-bindings: cache: Add docs for StarFive Starlink cache controller



Add DT binding documentation used by StarFive's
Starlink cache controller.

Signed-off-by: default avatarJoshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 1613e604
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive StarLink Cache Controller

maintainers:
  - Joshua Yeong <joshua.yeong@starfivetech.com>

description:
  StarFive's StarLink Cache Controller manages the L3 cache shared between
  clusters of CPU cores. The cache driver enables RISC-V non-standard cache
  management as an alternative to instructions in the RISC-V Zicbom extension.

allOf:
  - $ref: /schemas/cache-controller.yaml#

# We need a select here so we don't match all nodes with 'cache'
select:
  properties:
    compatible:
      contains:
        enum:
          - starfive,jh8100-starlink-cache

  required:
    - compatible

properties:
  compatible:
    items:
      - const: starfive,jh8100-starlink-cache
      - const: cache

  reg:
    maxItems: 1

unevaluatedProperties: false

required:
  - compatible
  - reg
  - cache-block-size
  - cache-level
  - cache-sets
  - cache-size
  - cache-unified

examples:
  - |
      soc {
        #address-cells = <2>;
        #size-cells = <2>;

        cache-controller@15000000 {
          compatible = "starfive,jh8100-starlink-cache", "cache";
          reg = <0x0 0x15000000 0x0 0x278>;
          cache-block-size = <64>;
          cache-level = <3>;
          cache-sets = <8192>;
          cache-size = <0x400000>;
          cache-unified;
        };
      };