Commit c61eda43 authored by Ivan Lipski's avatar Ivan Lipski Committed by Alex Deucher
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drm/amd/display: Check for S0i3 to be done before DCCG init on DCN21 



[WHY]
On DCN21, dccg2_init() is called in dcn10_init_hw() before
bios_golden_init(). During S0i3 resume, BIOS sets MICROSECOND_TIME_BASE_DIV
to 0x00120464 as a marker. dccg2_init() overwrites this to 0x00120264,
causing dcn21_s0i3_golden_init_wa() to misdetect the state and skip golden
init.
Eventually during the resume sequence, a flip timeout occurs.

[HOW]
Skip DCCG on dccg2_is_s0i3_golden_init_wa_done() on DCN21.

Fixes: 4c595e75 ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.")
Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarIvan Lipski <ivan.lipski@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8469dd5

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

+20 −1
Original line number Diff line number Diff line
@@ -96,6 +96,25 @@ static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl 
	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

}



/*

 * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to

 * 0x00120464 as a marker that golden init has already been done.

 * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init()

 * to decide whether to skip golden init.

 *

 * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to

 * 0x00120264, destroying the marker before it can be read.

 *

 * Guard the call: if the S0i3 marker is present, skip dccg2_init() so the

 * WA can function correctly. bios_golden_init() will handle init in that case.

 */

static void dccg21_init(struct dccg *dccg)

{

	if (dccg2_is_s0i3_golden_init_wa_done(dccg))

		return;



	dccg2_init(dccg);

}



static const struct dccg_funcs dccg21_funcs = {

	.update_dpp_dto = dccg21_update_dpp_dto,
@@ -103,7 +122,7 @@ static const struct dccg_funcs dccg21_funcs = { 
	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.otg_add_pixel = dccg2_otg_add_pixel,

	.otg_drop_pixel = dccg2_otg_drop_pixel,

	.dccg_init = dccg2_init,

	.dccg_init = dccg21_init,

	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */

	.allow_clock_gating = dccg2_allow_clock_gating,

	.enable_memory_low_power = dccg2_enable_memory_low_power,