Commit c76b766e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-02-09' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular weekly fixes, xe, amdgpu and msm are most of them, with some
  misc in i915, ivpu and nouveau, scattered but nothing too intense at
  this point.

  i915:
   - gvt: docs fix, uninit var, MAINTAINERS

  ivpu:
   - add aborted job status
   - disable d3 hot delay
   - mmu fixes

  nouveau:
   - fix gsp rpc size request
   - fix dma buffer leaks
   - use common code for gsp mem ctor

  xe:
   - Fix a loop in an error path
   - Fix a missing dma-fence reference
   - Fix a retry path on userptr REMAP
   - Workaround for a false gcc warning
   - Fix missing map of the usm batch buffer in the migrate vm.
   - Fix a memory leak.
   - Fix a bad assumption of used page size
   - Fix hitting a BUG() due to zero pages to map.
   - Remove some leftover async bind queue relics

  amdgpu:
   - Misc NULL/bounds check fixes
   - ODM pipe policy fix
   - Aborted suspend fixes
   - JPEG 4.0.5 fix
   - DCN 3.5 fixes
   - PSP fix
   - DP MST fix
   - Phantom pipe fix
   - VRAM vendor fix
   - Clang fix
   - SR-IOV fix

  msm:
   - DPU:
      - fix for kernel doc warnings and smatch warnings in dpu_encoder
      - fix for smatch warning in dpu_encoder
      - fix the bus bandwidth value for SDM670
   - DP:
      - fixes to handle unknown bpc case correctly for DP
      - fix for MISC0 programming
   - GPU:
      - dmabuf vmap fix
      - a610 UBWC corruption fix (incorrect hbb)
      - revert a commit that was making GPU recovery unreliable"

* tag 'drm-fixes-2024-02-09' of git://anongit.freedesktop.org/drm/drm: (43 commits)
  drm/xe: Remove TEST_VM_ASYNC_OPS_ERROR
  drm/xe/vm: don't ignore error when in_kthread
  drm/xe: Assume large page size if VMA not yet bound
  drm/xe/display: Fix memleak in display initialization
  drm/xe: Map both mem.kernel_bb_pool and usm.bb_pool
  drm/xe: circumvent bogus stringop-overflow warning
  drm/xe: Pick correct userptr VMA to repin on REMAP op failure
  drm/xe: Take a reference in xe_exec_queue_last_fence_get()
  drm/xe: Fix loop in vm_bind_ioctl_ops_unwind
  drm/amdgpu: Fix HDP flush for VFs on nbio v7.9
  drm/amd/display: Implement bounds check for stream encoder creation in DCN301
  drm/amd/display: Increase frame-larger-than for all display_mode_vba files
  drm/amd/display: Clear phantom stream count and plane count
  drm/amdgpu: Avoid fetching VRAM vendor info
  drm/amd/display: Disable ODM by default for DCN35
  drm/amd/display: Update phantom pipe enable / disable sequence
  drm/amd/display: Fix MST Null Ptr for RV
  drm/amdgpu: Fix shared buff copy to user
  drm/amd/display: Increase eval/entry delay for DCN35
  drm/amdgpu: remove asymmetrical irq disabling in jpeg 4.0.5 suspend
  ...
parents 1f719a2f 31152088

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -10801,11 +10801,11 @@ F: drivers/gpio/gpio-tangier.h 








INTEL GVT-g DRIVERS (Intel GPU Virtualization)









M:	Zhenyu Wang <zhenyuw@linux.intel.com>









M:	Zhi Wang <zhi.a.wang@intel.com>









M:	Zhi Wang <zhi.wang.linux@gmail.com>









L:	intel-gvt-dev@lists.freedesktop.org









L:	intel-gfx@lists.freedesktop.org









S:	Supported









W:	https://01.org/igvt-g









W:	https://github.com/intel/gvt-linux/wiki









T:	git https://github.com/intel/gvt-linux.git









F:	drivers/gpu/drm/i915/gvt/








































drivers/accel/ivpu/ivpu_drv.c



+2
−3






























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@@ -480,8 +480,7 @@ static int ivpu_pci_init(struct ivpu_device *vdev)







	/* Clear any pending errors */









	pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);



















	/* VPU 37XX does not require 10m D3hot delay */









	if (ivpu_hw_gen(vdev) == IVPU_HW_37XX)









	/* NPU does not require 10m D3hot delay */









	pdev->d3hot_delay = 0;



















	ret = pcim_enable_device(pdev);
































drivers/accel/ivpu/ivpu_fw.c



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−1






























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@@ -222,7 +222,6 @@ ivpu_fw_init_wa(struct ivpu_device *vdev)







	const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;



















	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||









	    (ivpu_hw_gen(vdev) > IVPU_HW_37XX) ||









	    (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))









		vdev->wa.disable_d0i3_msg = true;










































drivers/accel/ivpu/ivpu_hw_37xx.c



+1
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@@ -525,7 +525,7 @@ static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)







	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);



















	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);









	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);









	val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);









	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);



















	REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
































drivers/accel/ivpu/ivpu_hw_40xx.c



+1
−6






























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@@ -530,7 +530,7 @@ static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)







	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);



















	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);









	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);









	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);









	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);



















	REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);








@@ -704,7 +704,6 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)







{









	struct ivpu_hw_info *hw = vdev->hw;









	u32 tile_disable;









	u32 tile_enable;









	u32 fuse;



















	fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);








@@ -725,10 +724,6 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)







	else









		ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);



















	tile_enable = (~tile_disable) & TILE_MAX_MASK;



















	hw->sku = REG_SET_FLD_NUM(SKU, HW_ID, LNL_HW_ID, hw->sku);









	hw->sku = REG_SET_FLD_NUM(SKU, TILE, tile_enable, hw->sku);









	hw->tile_fuse = tile_disable;









	hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;