Commit c7a5aa4e authored Mar 28, 2024 by Andi Shyti

drm/i915/gt: Do not generate the command streamer for all the CCS



We want a fixed load CCS balancing consisting in all slices
sharing one single user engine. For this reason do not create the
intel_engine_cs structure with its dedicated command streamer for
CCS slices beyond the first.

Fixes: d2eae8e9 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: <stable@vger.kernel.org> # v6.2+
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328073409.674098-3-andi.shyti@linux.intel.com

parent f5d2904c

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+17 −0

Original line number	Diff line number	Diff line
		@@ -908,6 +908,23 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
		info->engine_mask &= ~BIT(GSC0);
		}

		/*
		* Do not create the command streamer for CCS slices beyond the first.
		* All the workload submitted to the first engine will be shared among
		* all the slices.
		*
		* Once the user will be allowed to customize the CCS mode, then this
		* check needs to be removed.
		*/
		if (IS_DG2(gt->i915)) {
		u8 first_ccs = __ffs(CCS_MASK(gt));

		/* Mask off all the CCS engine */
		info->engine_mask &= ~GENMASK(CCS3, CCS0);
		/* Put back in the first CCS engine */
		info->engine_mask \|= BIT(_CCS(first_ccs));
		}

		return info->engine_mask;
		}