Commit c85e209b authored by Frank Li's avatar Frank Li Committed by Alexandre Belloni
Browse files

i3c: master: svc: fix ibi may not return mandatory data byte 



MSTATUS[RXPEND] is only updated after the data transfer cycle started. This
creates an issue when the I3C clock is slow, and the CPU is running fast
enough that MSTATUS[RXPEND] may not be updated when the code reaches
checking point. As a result, mandatory data can be missed.

Add a wait for MSTATUS[COMPLETE] to ensure that all mandatory data is
already in FIFO. It also works without mandatory data.

Fixes: dd3c5284 ("i3c: master: svc: Add Silvaco I3C master driver")
Cc:  <stable@vger.kernel.org>
Reviewed-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20231023161658.3890811-4-Frank.Li@nxp.com


Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent 5e5e3c92

drivers/i3c/master/svc-i3c-master.c

+8 −0
Original line number Diff line number Diff line
@@ -333,6 +333,7 @@ static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, 
	struct i3c_ibi_slot *slot;

	unsigned int count;

	u32 mdatactrl;

	int ret, val;

	u8 *buf;



	slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
@@ -342,6 +343,13 @@ static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, 
	slot->len = 0;

	buf = slot->data;



	ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,

						SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000);

	if (ret) {

		dev_err(master->dev, "Timeout when polling for COMPLETE\n");

		return ret;

	}



	while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS))  &&

	       slot->len < SVC_I3C_FIFO_SIZE) {

		mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);