Commit c8a346e4 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs 



Arm heterogeneous configurations should have separate PMU nodes for each
CPU uarch as the uarch specific events can be different. The
"arm,armv8-pmuv3" compatible is also intended for s/w models rather than
specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by: default avatar"Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20240417204247.3216703-1-robh@kernel.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 839936d9

arch/arm64/boot/dts/qcom/msm8956.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -8,8 +8,8 @@ 


#include "msm8976.dtsi"



&pmu {

	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;

&pmu_a72 {

	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;

};



&tsens {

arch/arm64/boot/dts/qcom/msm8976.dtsi

+9 −3
Original line number Diff line number Diff line
@@ -222,11 +222,17 @@ memory@80000000 { 
		reg = <0x0 0x80000000 0x0 0x0>;

	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

	pmu-a53 {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	pmu_a72: pmu-a72 {

		compatible = "arm,cortex-a72-pmu";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;

	};





	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

arch/arm64/boot/dts/qcom/sm4450.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -292,9 +292,14 @@ memory@a0000000 { 
		reg = <0x0 0xa0000000 0x0 0x0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	pmu-a55 {

		compatible = "arm,cortex-a55-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-a78 {

		compatible = "arm,cortex-a78-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	psci {

arch/arm64/boot/dts/qcom/sm8350.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -301,8 +301,18 @@ memory@80000000 { 
		reg = <0x0 0x80000000 0x0 0x0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

	pmu-a55 {

		compatible = "arm,cortex-a55-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-a78 {

		compatible = "arm,cortex-a78-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-x1 {

		compatible = "arm,cortex-x1-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};

arch/arm64/boot/dts/qcom/sm8550.dtsi

+17 −2
Original line number Diff line number Diff line
@@ -352,8 +352,23 @@ memory@a0000000 { 
		reg = <0 0xa0000000 0 0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

	pmu-a510 {

		compatible = "arm,cortex-a510-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-a710 {

		compatible = "arm,cortex-a710-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-a715 {

		compatible = "arm,cortex-a715-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu-x3 {

		compatible = "arm,cortex-x3-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};