Unverified Commit c8f7de01 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-dt64-6.20-2' of... 

Merge tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.20, part two

Add DPU clock management unit nodes to Google GS101.

* tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux

:
  arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes
  dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
  dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9587fe49 024d8f4a

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

+20 −1
Original line number Diff line number Diff line
@@ -29,9 +29,10 @@ properties: 
    enum:

      - google,gs101-cmu-top

      - google,gs101-cmu-apm

      - google,gs101-cmu-misc

      - google,gs101-cmu-dpu

      - google,gs101-cmu-hsi0

      - google,gs101-cmu-hsi2

      - google,gs101-cmu-misc

      - google,gs101-cmu-peric0

      - google,gs101-cmu-peric1
@@ -77,6 +78,24 @@ allOf: 
          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            const: google,gs101-cmu-dpu



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24.576 MHz)

            - description: DPU bus clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus



  - if:

      properties:

        compatible:

arch/arm64/boot/dts/exynos/google/gs101.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -1815,6 +1815,23 @@ pinctrl_gsacore: pinctrl@17a80000 { 
			status = "disabled";

		};



		cmu_dpu: clock-controller@1c000000 {

			compatible = "google,gs101-cmu-dpu";

			reg = <0x1c000000 0x10000>;

			#clock-cells = <1>;



			clocks = <&ext_24_5m>,

				 <&cmu_top CLK_DOUT_CMU_DPU_BUS>;

			clock-names = "oscclk", "bus";

			samsung,sysreg = <&sysreg_dpu>;

		};



		sysreg_dpu: syscon@1c020000 {

			compatible = "google,gs101-dpu-sysreg", "syscon";

			reg = <0x1c020000 0x10000>;

			clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;

		};



		cmu_top: clock-controller@1e080000 {

			compatible = "google,gs101-cmu-top";

			reg = <0x1e080000 0x10000>;

include/dt-bindings/clock/google,gs101.h

+36 −0
Original line number Diff line number Diff line
@@ -313,6 +313,42 @@ 
#define CLK_APM_PLL_DIV4_APM				70

#define CLK_APM_PLL_DIV16_APM				71



/* CMU_DPU */

#define CLK_MOUT_DPU_BUS_USER				1

#define CLK_DOUT_DPU_BUSP				2

#define CLK_GOUT_DPU_PCLK				3

#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK			4

#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM		5

#define CLK_GOUT_DPU_DPUF_ACLK_DMA			6

#define CLK_GOUT_DPU_DPUF_ACLK_DPP			7

#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK			8

#define CLK_GOUT_DPU_GPC_DPU_PCLK			9

#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK		10

#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK		11

#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK		12

#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK		13

#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK			14

#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK			15

#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK			16

#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK			17

#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK			18

#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK			19

#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK			20

#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK			21

#define CLK_GOUT_DPU_SSMT_DPU0_ACLK			22

#define CLK_GOUT_DPU_SSMT_DPU0_PCLK			23

#define CLK_GOUT_DPU_SSMT_DPU1_ACLK			24

#define CLK_GOUT_DPU_SSMT_DPU1_PCLK			25

#define CLK_GOUT_DPU_SSMT_DPU2_ACLK			26

#define CLK_GOUT_DPU_SSMT_DPU2_PCLK			27

#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1		28

#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2		29

#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1		30

#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2		31

#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1		32

#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2		33

#define CLK_GOUT_DPU_SYSREG_DPU_PCLK			34



/* CMU_HSI0 */

#define CLK_FOUT_USB_PLL					1

#define CLK_MOUT_PLL_USB					2