Commit c925e993 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.15-2025-04-16' of... 

Merge tag 'amd-drm-fixes-6.15-2025-04-16' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.15-2025-04-16:

amdgpu:
- Cleaner shader sysfs fix
- Suspend fix
- Fix doorbell free ordering
- Video caps fix
- DML2 memory allocation optimization
- HDP fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250416223137.1146653-1-alexander.deucher@amd.com
parents 8ffd015d c235a713

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1123,6 +1123,7 @@ struct amdgpu_device { 
	bool				in_s3;

	bool				in_s4;

	bool				in_s0ix;

	suspend_state_t			last_suspend_state;



	enum pp_mp1_state               mp1_state;

	struct amdgpu_doorbell_index doorbell_index;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -3510,6 +3510,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
			amdgpu_device_mem_scratch_fini(adev);

			amdgpu_ib_pool_fini(adev);

			amdgpu_seq64_fini(adev);

			amdgpu_doorbell_fini(adev);

		}

		if (adev->ip_blocks[i].version->funcs->sw_fini) {

			r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);
@@ -4858,7 +4859,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) 


		iounmap(adev->rmmio);

		adev->rmmio = NULL;

		amdgpu_doorbell_fini(adev);

		drm_dev_exit(idx);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+13 −1
Original line number Diff line number Diff line
@@ -2548,8 +2548,20 @@ static int amdgpu_pmops_suspend(struct device *dev) 
		adev->in_s0ix = true;

	else if (amdgpu_acpi_is_s3_active(adev))

		adev->in_s3 = true;

	if (!adev->in_s0ix && !adev->in_s3)

	if (!adev->in_s0ix && !adev->in_s3) {

		/* don't allow going deep first time followed by s2idle the next time */

		if (adev->last_suspend_state != PM_SUSPEND_ON &&

		    adev->last_suspend_state != pm_suspend_target_state) {

			drm_err_once(drm_dev, "Unsupported suspend state %d\n",

				     pm_suspend_target_state);

			return -EINVAL;

		}

		return 0;

	}



	/* cache the state last used for suspend */

	adev->last_suspend_state = pm_suspend_target_state;



	return amdgpu_device_suspend(drm_dev, true);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+11 −3
Original line number Diff line number Diff line
@@ -1438,9 +1438,11 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;

	struct drm_gpu_scheduler *sched = &ring->sched;

	struct drm_sched_entity entity;

	static atomic_t counter;

	struct dma_fence *f;

	struct amdgpu_job *job;

	struct amdgpu_ib *ib;

	void *owner;

	int i, r;



	/* Initialize the scheduler entity */
@@ -1451,9 +1453,15 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) 
		goto err;

	}



	r = amdgpu_job_alloc_with_ib(ring->adev, &entity, NULL,

				     64, 0,

				     &job);

	/*

	 * Use some unique dummy value as the owner to make sure we execute

	 * the cleaner shader on each submission. The value just need to change

	 * for each submission and is otherwise meaningless.

	 */

	owner = (void *)(unsigned long)atomic_inc_return(&counter);



	r = amdgpu_job_alloc_with_ib(ring->adev, &entity, owner,

				     64, 0, &job);

	if (r)

		goto err;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -6114,7 +6114,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->hdp.funcs->flush_hdp(adev, NULL);

		amdgpu_device_flush_hdp(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -6192,7 +6192,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->hdp.funcs->flush_hdp(adev, NULL);

		amdgpu_device_flush_hdp(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -6269,7 +6269,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->hdp.funcs->flush_hdp(adev, NULL);

		amdgpu_device_flush_hdp(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6644,7 +6644,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 
	}



	if (amdgpu_emu_mode == 1)

		adev->hdp.funcs->flush_hdp(adev, NULL);

		amdgpu_device_flush_hdp(adev, NULL);



	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);