Commit c9517783 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Drop Wa_16011777198 



Wa_16011777198 only applies to pre-production steppings of DG2, which
we're no longer supporting.  Remove the workaround and override_gucrc
handling, which is no longer needed.  Since this was the final use of
IS_DG2_GRAPHICS_STEP, that macro can also be removed now.

v2:
 - Include the promised removal of override_gucrc handling.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230816214824.548575-2-matthew.d.roper@intel.com
parent f1c80571

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

+0 −63
Original line number Diff line number Diff line
@@ -138,17 +138,6 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value) 
	return ret > 0 ? -EPROTO : ret;

}



static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)

{

	u32 request[] = {

		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,

		SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),

		id,

	};



	return intel_guc_send(guc, request, ARRAY_SIZE(request));

}



static bool slpc_is_running(struct intel_guc_slpc *slpc)

{

	return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -199,15 +188,6 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value) 
	return ret;

}



static int slpc_unset_param(struct intel_guc_slpc *slpc, u8 id)

{

	struct intel_guc *guc = slpc_to_guc(slpc);



	GEM_BUG_ON(id >= SLPC_MAX_PARAM);



	return guc_action_slpc_unset_param(guc, id);

}



static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)

{

	struct intel_guc *guc = slpc_to_guc(slpc);
@@ -672,49 +652,6 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc) 
		slpc->boost_freq = slpc->rp0_freq;

}



/**

 * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode

 * @slpc: pointer to intel_guc_slpc.

 * @mode: new value of the mode.

 *

 * This function will override the GUCRC mode.

 *

 * Return: 0 on success, non-zero error code on failure.

 */

int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)

{

	int ret;

	struct drm_i915_private *i915 = slpc_to_i915(slpc);

	intel_wakeref_t wakeref;



	if (mode >= SLPC_GUCRC_MODE_MAX)

		return -EINVAL;



	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {

		ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);

		if (ret)

			guc_err(slpc_to_guc(slpc), "Override RC mode %d failed: %pe\n",

				mode, ERR_PTR(ret));

	}



	return ret;

}



int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)

{

	struct drm_i915_private *i915 = slpc_to_i915(slpc);

	intel_wakeref_t wakeref;

	int ret = 0;



	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {

		ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);

		if (ret)

			guc_err(slpc_to_guc(slpc), "Unsetting RC mode failed: %pe\n", ERR_PTR(ret));

	}



	return ret;

}



/*

 * intel_guc_slpc_enable() - Start SLPC

 * @slpc: pointer to intel_guc_slpc.

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h

+0 −2
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val); 
void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);

void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);

void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);

int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);

int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);

int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);



#endif

drivers/gpu/drm/i915/i915_drv.h

+0 −19
Original line number Diff line number Diff line
@@ -698,25 +698,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
	(IS_METEORLAKE(__i915) && \

	 IS_MEDIA_STEP(__i915, since, until))



/*

 * DG2 hardware steppings are a bit unusual.  The hardware design was forked to

 * create three variants (G10, G11, and G12) which each have distinct

 * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT

 * stepping back to "A0" for their first iterations, even though they're more

 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of

 * functionality and workarounds.  However the display stepping does not reset

 * in the same manner --- a specific stepping like "B0" has a consistent

 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.

 *

 * TLDR:  All GT workarounds and stepping-specific logic must be applied in

 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds

 * and stepping-specific logic will be applied with a general DG2-wide stepping

 * number.

 */

#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \

	(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \

	 IS_GRAPHICS_STEP(__i915, since, until))



#define IS_DG2_DISPLAY_STEP(__i915, since, until) \

	(IS_DG2(__i915) && \

	 IS_DISPLAY_STEP(__i915, since, until))

drivers/gpu/drm/i915/i915_perf.c

+0 −32
Original line number Diff line number Diff line
@@ -1675,13 +1675,6 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) 


	free_oa_buffer(stream);



	/*

	 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.

	 */

	if (stream->override_gucrc)

		drm_WARN_ON(&gt->i915->drm,

			    intel_guc_slpc_unset_gucrc_mode(&gt->uc.guc.slpc));



	intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);

	intel_engine_pm_put(stream->engine);
@@ -3272,7 +3265,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, 
	struct drm_i915_private *i915 = stream->perf->i915;

	struct i915_perf *perf = stream->perf;

	struct i915_perf_group *g;

	struct intel_gt *gt;

	int ret;



	if (!props->engine) {
@@ -3280,7 +3272,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, 
			"OA engine not specified\n");

		return -EINVAL;

	}

	gt = props->engine->gt;

	g = props->engine->oa_group;



	/*
@@ -3381,25 +3372,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, 
	intel_engine_pm_get(stream->engine);

	intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);



	/*

	 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes

	 * OA to lose the configuration state. Prevent this by overriding GUCRC

	 * mode.

	 */

	if (intel_uc_uses_guc_rc(&gt->uc) &&

	    (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||

	     IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {

		ret = intel_guc_slpc_override_gucrc_mode(&gt->uc.guc.slpc,

							 SLPC_GUCRC_MODE_GUCRC_NO_RC6);

		if (ret) {

			drm_dbg(&stream->perf->i915->drm,

				"Unable to override gucrc mode\n");

			goto err_gucrc;

		}



		stream->override_gucrc = true;

	}



	ret = alloc_oa_buffer(stream);

	if (ret)

		goto err_oa_buf_alloc;
@@ -3436,10 +3408,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, 
	free_oa_buffer(stream);



err_oa_buf_alloc:

	if (stream->override_gucrc)

		intel_guc_slpc_unset_gucrc_mode(&gt->uc.guc.slpc);



err_gucrc:

	intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);

	intel_engine_pm_put(stream->engine);

drivers/gpu/drm/i915/i915_perf_types.h

+0 −6
Original line number Diff line number Diff line
@@ -338,12 +338,6 @@ struct i915_perf_stream { 
	 * buffer should be checked for available data.

	 */

	u64 poll_oa_period;



	/**

	 * @override_gucrc: GuC RC has been overridden for the perf stream,

	 * and we need to restore the default configuration on release.

	 */

	bool override_gucrc;

};



/**