Commit c9ac071e authored by Eric Huang's avatar Eric Huang Committed by Ping-Ke Shih
Browse files

wifi: rtw89: use frequency domain RSSI



To get more accurate RSSI, this commit includes frequency domain RSSI
info in RSSI calculation. Add correspond physts parsing and macro to
get frequency domain RSSI information for supported IC.

Signed-off-by: default avatarEric Huang <echuang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20240828055217.10263-3-pkshih@realtek.com
parent 9ecb64ed
Loading
Loading
Loading
Loading
+72 −1
Original line number Diff line number Diff line
@@ -1583,11 +1583,27 @@ static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
	return ie_len;
}

static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
						const struct rtw89_phy_sts_iehdr *iehdr,
						struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_ie01_v2 *ie;
	u8 *rpl_fd = phy_ppdu->rpl_fd;

	ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
	rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
	rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
	rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
	rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);

	phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
}

static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
					     const struct rtw89_phy_sts_iehdr *iehdr,
					     struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr;
	const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
	s16 cfo;
	u32 t;

@@ -1598,12 +1614,17 @@ static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
		phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
	}

	if (!phy_ppdu->hdr_2_en)
		phy_ppdu->rx_path_en =
			le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);

	if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
		return;

	if (!phy_ppdu->to_self)
		return;

	phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
	phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
	phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
	phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
@@ -1619,6 +1640,39 @@ static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
	}

	rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);

	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
		rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
}

static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
					     const struct rtw89_phy_sts_iehdr *iehdr,
					     struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
	u16 tmp_rpl;

	tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
	phy_ppdu->rpl_avg = tmp_rpl >> 1;
}

static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
						const struct rtw89_phy_sts_iehdr *iehdr,
						struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_ie00_v2 *ie;
	u8 *rpl_path = phy_ppdu->rpl_path;
	u16 tmp_rpl[RF_PATH_MAX];
	u8 i;

	ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
	tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
	tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
	tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
	tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);

	for (i = 0; i < RF_PATH_MAX; i++)
		rpl_path[i] = tmp_rpl[i] >> 1;
}

static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
@@ -1630,6 +1684,11 @@ static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
	ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);

	switch (ie) {
	case RTW89_PHYSTS_IE00_CMN_CCK:
		rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
		if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
			rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
		break;
	case RTW89_PHYSTS_IE01_CMN_OFDM:
		rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
		break;
@@ -1640,6 +1699,13 @@ static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
	return 0;
}

static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;

	phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
}

static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
@@ -1651,6 +1717,10 @@ static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
	rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
	rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
	rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);

	phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
	if (phy_ppdu->hdr_2_en)
		rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
}

static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
@@ -1703,6 +1773,7 @@ static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
		}
	}

	rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
	rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);

	return 0;
+17 −0
Original line number Diff line number Diff line
@@ -797,6 +797,11 @@ struct rtw89_rx_phy_ppdu {
	u8 chan_idx;
	u8 ie;
	u16 rate;
	u8 rpl_avg;
	u8 rpl_path[RF_PATH_MAX];
	u8 rpl_fd[RF_PATH_MAX];
	u8 bw_idx;
	u8 rx_path_en;
	struct {
		bool has;
		u8 avg_snr;
@@ -809,6 +814,7 @@ struct rtw89_rx_phy_ppdu {
	bool stbc;
	bool to_self;
	bool valid;
	bool hdr_2_en;
};

enum rtw89_mac_idx {
@@ -3613,6 +3619,8 @@ struct rtw89_chip_ops {
	void (*query_ppdu)(struct rtw89_dev *rtwdev,
			   struct rtw89_rx_phy_ppdu *phy_ppdu,
			   struct ieee80211_rx_status *status);
	void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
				    struct rtw89_rx_phy_ppdu *phy_ppdu);
	void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
				enum rtw89_phy_idx phy_idx);
	void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
@@ -6307,6 +6315,15 @@ static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
}

static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
						  struct rtw89_rx_phy_ppdu *phy_ppdu)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;

	if (chip->ops->convert_rpl_to_rssi)
		chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
}

static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
					 enum rtw89_phy_idx phy_idx)
{
+1 −0
Original line number Diff line number Diff line
@@ -2387,6 +2387,7 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = {
	.get_thermal		= rtw8851b_get_thermal,
	.ctrl_btg_bt_rx		= rtw8851b_ctrl_btg_bt_rx,
	.query_ppdu		= rtw8851b_query_ppdu,
	.convert_rpl_to_rssi	= NULL,
	.ctrl_nbtg_bt_tx	= rtw8851b_ctrl_nbtg_bt_tx,
	.cfg_txrx_path		= rtw8851b_bb_cfg_txrx_path,
	.set_txpwr_ul_tb_offset	= rtw8851b_set_txpwr_ul_tb_offset,
+1 −0
Original line number Diff line number Diff line
@@ -2113,6 +2113,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
	.get_thermal		= rtw8852a_get_thermal,
	.ctrl_btg_bt_rx		= rtw8852a_ctrl_btg_bt_rx,
	.query_ppdu		= rtw8852a_query_ppdu,
	.convert_rpl_to_rssi	= NULL,
	.ctrl_nbtg_bt_tx	= rtw8852a_ctrl_nbtg_bt_tx,
	.cfg_txrx_path		= NULL,
	.set_txpwr_ul_tb_offset	= rtw8852a_set_txpwr_ul_tb_offset,
+1 −0
Original line number Diff line number Diff line
@@ -741,6 +741,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
	.get_thermal		= rtw8852bx_get_thermal,
	.ctrl_btg_bt_rx		= rtw8852bx_ctrl_btg_bt_rx,
	.query_ppdu		= rtw8852bx_query_ppdu,
	.convert_rpl_to_rssi	= rtw8852bx_convert_rpl_to_rssi,
	.ctrl_nbtg_bt_tx	= rtw8852bx_ctrl_nbtg_bt_tx,
	.cfg_txrx_path		= rtw8852bx_bb_cfg_txrx_path,
	.set_txpwr_ul_tb_offset	= rtw8852bx_set_txpwr_ul_tb_offset,
Loading