Commit ca1de841 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v6.15-rockchip-clk1' of... 

Merge tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - New clock controller drivers for Rockchip rk3528 and rk3562
 - Fix a parent for Rockchip rk3328 clk_ref_usb3otg
 - Add camera interface clocks for Rockchip rk3188

* tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: Add clock controller for the RK3562
  dt-bindings: clock: Add RK3562 cru
  clk: rockchip: rk3528: Add reset lookup table
  clk: rockchip: Add clock controller driver for RK3528 SoC
  clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
  dt-bindings: clock: Document clock and reset unit of RK3528
  clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent
  clk: rockchip: rk3568: mark hclk_vi as critical
  clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
  dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1
parents 2014c95a f863d4cc

Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3528 Clock and Reset Controller



maintainers:

  - Yao Zi <ziyao@disroot.org>



description: |

  The RK3528 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example, it provides SCLK_UART0 and

  PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART

  module.

  Each clock is assigned an identifier, consumer nodes can use it to specify

  the clock. All available clock and reset IDs are defined in dt-binding

  headers.



properties:

  compatible:

    const: rockchip,rk3528-cru



  reg:

    maxItems: 1



  clocks:

    items:

      - description: External 24MHz oscillator clock

      - description: >

          50MHz clock generated by PHY module, for generating GMAC0 clocks only.



  clock-names:

    items:

      - const: xin24m

      - const: gmac0



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@ff4a0000 {

        compatible = "rockchip,rk3528-cru";

        reg = <0xff4a0000 0x30000>;

        clocks = <&xin24m>, <&gmac0_clk>;

        clock-names = "xin24m", "gmac0";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip rk3562 Clock and Reset Control Module



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description:

  The RK3562 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example it provides SCLK_UART2 and

  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART

  module.



properties:

  compatible:

    const: rockchip,rk3562-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: xin24m

      - const: xin32k



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@ff100000 {

      compatible = "rockchip,rk3562-cru";

      reg = <0xff100000 0x40000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

drivers/clk/rockchip/Kconfig

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@@ -93,6 +93,20 @@ config CLK_RK3399 
	help

	  Build the driver for RK3399 Clock Driver.



config CLK_RK3528

	bool "Rockchip RK3528 clock controller support"

	depends on ARM64 || COMPILE_TEST

	default y

	help

	  Build the driver for RK3528 Clock Controller.



config CLK_RK3562

	bool "Rockchip RK3562 clock controller support"

	depends on ARM64 || COMPILE_TEST

	default y

	help

	  Build the driver for RK3562 Clock Controller.



config CLK_RK3568

	bool "Rockchip RK3568 clock controller support"

	depends on ARM64 || COMPILE_TEST

drivers/clk/rockchip/Makefile

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@@ -28,6 +28,8 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o 
obj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o

obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o

obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o

obj-$(CONFIG_CLK_RK3528)	+= clk-rk3528.o rst-rk3528.o

obj-$(CONFIG_CLK_RK3562)	+= clk-rk3562.o rst-rk3562.o

obj-$(CONFIG_CLK_RK3568)	+= clk-rk3568.o

obj-$(CONFIG_CLK_RK3576)	+= clk-rk3576.o rst-rk3576.o

obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o rst-rk3588.o

drivers/clk/rockchip/clk-pll.c

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@@ -204,11 +204,13 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 
	rockchip_rk3036_pll_get_params(pll, &cur);

	cur.rate = 0;



	if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {

		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);

		if (cur_parent == PLL_MODE_NORM) {

			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);

			rate_change_remuxed = 1;

		}

	}



	/* update pll values */

	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,