Commit ca243e65 authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
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clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock 



The alternate parent clock for this mux is mout_pll_usb, not the pll
itself.

Fixes: 1891e4d4 ("clk: samsung: gs101: add support for cmu_hsi0")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250603-samsung-clk-fixes-v1-2-49daf1ff4592@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 29a9361f

drivers/clk/samsung/clk-gs101.c

+1 −1
Original line number Diff line number Diff line
@@ -2129,7 +2129,7 @@ PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk", 
					    "dout_cmu_hsi0_usbdpdbg" };

PNAME(mout_hsi0_bus_p)			= { "mout_hsi0_bus_user",

					    "mout_hsi0_alt_user" };

PNAME(mout_hsi0_usb20_ref_p)		= { "fout_usb_pll",

PNAME(mout_hsi0_usb20_ref_p)		= { "mout_pll_usb",

					    "mout_hsi0_tcxo_user" };

PNAME(mout_hsi0_usb31drd_p)		= { "fout_usb_pll",

					    "mout_hsi0_usb31drd_user",