Commit cb4046d2 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: Drop dead code for xehpsdv 



PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.

The registers not used anymore are also removed.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarTvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-2-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 962601ac

Documentation/gpu/rfc/i915_vm_bind.h

+5 −6
Original line number Diff line number Diff line
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence { 
 * Multiple VA mappings can be created to the same section of the object

 * (aliasing).

 *

 * The @start, @offset and @length must be 4K page aligned. However the DG2

 * and XEHPSDV has 64K page size for device local memory and has compact page

 * table. On those platforms, for binding device local-memory objects, the

 * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix

 * the local memory 64K page and the system memory 4K page bindings in the same

 * 2M range.

 * The @start, @offset and @length must be 4K page aligned. However the DG2 has

 * 64K page size for device local memory and has compact page table. On that

 * platform, for binding device local-memory objects, the @start, @offset and

 * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K

 * page and the system memory 4K page bindings in the same 2M range.

 *

 * Error code -EINVAL will be returned if @start, @offset and @length are not

 * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

+20 −20
Original line number Diff line number Diff line
@@ -500,7 +500,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, 
}



static void

xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,

xehp_ppgtt_insert_huge(struct i915_address_space *vm,

		       struct i915_vma_resource *vma_res,

		       struct sgt_dma *iter,

		       unsigned int pat_index,
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm, 
	struct sgt_dma iter = sgt_dma(vma_res);



	if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {

		if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))

			xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);

		if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))

			xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);

		else

			gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);

	} else  {
@@ -781,7 +781,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, 
	drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));

}



static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,

static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,

				       dma_addr_t addr,

				       u64 offset,

				       unsigned int pat_index,
@@ -810,14 +810,14 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, 
	vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);

}



static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,

static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,

				    dma_addr_t addr,

				    u64 offset,

				    unsigned int pat_index,

				    u32 flags)

{

	if (flags & PTE_LM)

		return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,

		return xehp_ppgtt_insert_entry_lm(vm, addr, offset,

						  pat_index, flags);



	return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
@@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, 
	ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;

	ppgtt->vm.insert_entries = gen8_ppgtt_insert;

	if (HAS_64K_PAGES(gt->i915))

		ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;

		ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;

	else

		ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;

	ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;

drivers/gpu/drm/i915/gt/intel_gsc.c

+0 −15
Original line number Diff line number Diff line
@@ -103,19 +103,6 @@ static const struct gsc_def gsc_def_dg1[] = { 
	}

};



static const struct gsc_def gsc_def_xehpsdv[] = {

	{

		/* HECI1 not enabled on the device. */

	},

	{

		.name = "mei-gscfi",

		.bar = DG1_GSC_HECI2_BASE,

		.bar_size = GSC_BAR_LENGTH,

		.use_polling = true,

		.slow_firmware = true,

	}

};



static const struct gsc_def gsc_def_dg2[] = {

	{

		.name = "mei-gsc",
@@ -188,8 +175,6 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc, 


	if (IS_DG1(i915)) {

		def = &gsc_def_dg1[intf_id];

	} else if (IS_XEHPSDV(i915)) {

		def = &gsc_def_xehpsdv[intf_id];

	} else if (IS_DG2(i915)) {

		def = &gsc_def_dg2[intf_id];

	} else {

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+2 −18
Original line number Diff line number Diff line
@@ -57,24 +57,12 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = { 
 * are of a "GAM" subclass that has special rules.  Thus we use a separate

 * GAM table farther down for those.

 */

static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {

static const struct intel_mmio_range dg2_mslice_steering_table[] = {

	{ 0x00DD00, 0x00DDFF },

	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */

	{},

};



static const struct intel_mmio_range xehpsdv_gam_steering_table[] = {

	{ 0x004000, 0x004AFF },

	{ 0x00C800, 0x00CFFF },

	{},

};



static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {

	{ 0x00B000, 0x00B0FF },

	{ 0x00D800, 0x00D8FF },

	{},

};



static const struct intel_mmio_range dg2_lncf_steering_table[] = {

	{ 0x00B000, 0x00B0FF },

	{ 0x00D880, 0x00D8FF },
@@ -188,17 +176,13 @@ void intel_gt_mcr_init(struct intel_gt *gt) 
	} else if (IS_PONTEVECCHIO(i915)) {

		gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;

	} else if (IS_DG2(i915)) {

		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;

		gt->steering_table[MSLICE] = dg2_mslice_steering_table;

		gt->steering_table[LNCF] = dg2_lncf_steering_table;

		/*

		 * No need to hook up the GAM table since it has a dedicated

		 * steering control register on DG2 and can use implicit

		 * steering.

		 */

	} else if (IS_XEHPSDV(i915)) {

		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;

		gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;

		gt->steering_table[GAM] = xehpsdv_gam_steering_table;

	} else if (GRAPHICS_VER(i915) >= 11 &&

		   GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {

		gt->steering_table[L3BANK] = icl_l3bank_steering_table;

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+0 −50
Original line number Diff line number Diff line
@@ -718,44 +718,11 @@ 


#define UNSLICE_UNIT_LEVEL_CLKGATE		_MMIO(0x9434)

#define   VFUNIT_CLKGATE_DIS			REG_BIT(20)

#define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */

#define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */

#define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)

#define   HSUNIT_CLKGATE_DIS			REG_BIT(8)

#define   VSUNIT_CLKGATE_DIS			REG_BIT(3)



#define UNSLCGCTL9440				_MMIO(0x9440)

#define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)

#define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)

#define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)

#define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)

#define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)

#define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)

#define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)

#define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)

#define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)

#define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)

#define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)

#define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)



#define UNSLCGCTL9444				_MMIO(0x9444)

#define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)

#define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)

#define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)

#define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)

#define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)

#define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)

#define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)

#define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)

#define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)

#define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)

#define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)

#define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)

#define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)

#define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)

#define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)

#define   LTCDD_CLKGATE_DIS			REG_BIT(10)



#define GEN11_SLICE_UNIT_LEVEL_CLKGATE		_MMIO(0x94d4)

#define XEHP_SLICE_UNIT_LEVEL_CLKGATE		MCR_REG(0x94d4)

#define   SARBUNIT_CLKGATE_DIS			(1 << 5)
@@ -765,9 +732,6 @@ 
#define   L3_CLKGATE_DIS			REG_BIT(16)

#define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)



#define SCCGCTL94DC				MCR_REG(0x94dc)

#define   CG3DDISURB				REG_BIT(14)



#define UNSLICE_UNIT_LEVEL_CLKGATE2		_MMIO(0x94e4)

#define   VSUNIT_CLKGATE_DIS_TGL		REG_BIT(19)

#define   PSDUNIT_CLKGATE_DIS			REG_BIT(5)
@@ -1046,9 +1010,6 @@ 
#define XEHP_L3SQCREG5				MCR_REG(0xb158)

#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)



#define MLTICTXCTL				MCR_REG(0xb170)

#define   TDONRENDER				REG_BIT(2)



#define XEHP_L3SCQREG7				MCR_REG(0xb188)

#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
@@ -1057,9 +1018,6 @@ 
#define   SCRUB_RATE_PER_BANK_MASK		REG_GENMASK(2, 0)

#define   SCRUB_RATE_4B_PER_CLK			REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)



#define L3SQCREG1_CCS0				MCR_REG(0xb200)

#define   FLUSHALLNONCOH			REG_BIT(5)



#define GEN11_GLBLINVL				_MMIO(0xb404)

#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)

#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
@@ -1109,7 +1067,6 @@ 
#define XEHP_COMPCTX_TLB_INV_CR			MCR_REG(0xcf04)

#define XELPMP_GSC_TLB_INV_CR			_MMIO(0xcf04)   /* media GT only */



#define XEHP_MERT_MOD_CTRL			MCR_REG(0xcf28)

#define RENDER_MOD_CTRL				MCR_REG(0xcf2c)

#define COMP_MOD_CTRL				MCR_REG(0xcf30)

#define XELPMP_GSC_MOD_CTRL			_MMIO(0xcf30)	/* media GT only */
@@ -1185,7 +1142,6 @@ 
#define EU_PERF_CNTL4				PERF_REG(0xe45c)



#define GEN9_ROW_CHICKEN4			MCR_REG(0xe48c)

#define   GEN12_DISABLE_GRF_CLEAR		REG_BIT(13)

#define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)

#define   GEN12_DISABLE_TDL_PUSH		REG_BIT(9)

#define   GEN11_DIS_PICK_2ND_EU			REG_BIT(7)
@@ -1202,7 +1158,6 @@ 
#define   FLOW_CONTROL_ENABLE			REG_BIT(15)

#define   UGM_BACKUP_MODE			REG_BIT(13)

#define   MDQ_ARBITRATION_MODE			REG_BIT(12)

#define   SYSTOLIC_DOP_CLOCK_GATING_DIS		REG_BIT(10)

#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	REG_BIT(8)

#define   STALL_DOP_GATING_DISABLE		REG_BIT(5)

#define   THROTTLE_12_5				REG_GENMASK(4, 2)
@@ -1679,11 +1634,6 @@ 


#define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)



#define GT0_PACKAGE_ENERGY_STATUS		_MMIO(0x250004)

#define GT0_PACKAGE_RAPL_LIMIT			_MMIO(0x250008)

#define GT0_PACKAGE_POWER_SKU_UNIT		_MMIO(0x250068)

#define GT0_PLATFORM_ENERGY_STATUS		_MMIO(0x25006c)



/*

 * Standalone Media's non-engine GT registers are located at their regular GT

 * offsets plus 0x380000.  This extra offset is stored inside the intel_uncore