Commit cb467c45 authored by Amelie Delaunay's avatar Amelie Delaunay Committed by Vinod Koul
Browse files

dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses 



Current behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1
for the remainder without optimization.

New behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1 for
(x * chan->max_burst) + 1 for the remainder.
Depending on channel FIFO size, optimal double-word (word if only 8-byte
FIFO size) bursts can be programmed before managing the very last remainder
with lower data width.
In case of _prep_slave_sg, and depending on the channel Transfer Complete
event configuration, the user is warned about the refactored linked-list,
not having the same items count than the initial sg_list. This warning is
shown only if the configuration is successful.

Signed-off-by: default avatarAmelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-3-8311fe6f228d@foss.st.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 12eb621e

drivers/dma/stm32/stm32-dma3.c

+33 −7
Original line number Diff line number Diff line
@@ -1126,6 +1126,25 @@ static void stm32_dma3_free_chan_resources(struct dma_chan *c) 
	chan->config_set = 0;

}



static u32 stm32_dma3_get_ll_count(struct stm32_dma3_chan *chan, size_t len)

{

	u32 count;



	count = len / STM32_DMA3_MAX_BLOCK_SIZE;

	len -= (len / STM32_DMA3_MAX_BLOCK_SIZE) * STM32_DMA3_MAX_BLOCK_SIZE;



	if (len >= chan->max_burst) {

		count += 1; /* len < STM32_DMA3_MAX_BLOCK_SIZE here, so it fits in one item */

		len -= (len / chan->max_burst) * chan->max_burst;

	}



	/* Unaligned remainder fits in one extra item */

	if (len > 0)

		count += 1;



	return count;

}



static void stm32_dma3_init_chan_config_for_memcpy(struct stm32_dma3_chan *chan,

						   dma_addr_t dst, dma_addr_t src)

{
@@ -1161,7 +1180,7 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha 
	size_t next_size, offset;

	u32 count, i, ctr1, ctr2;



	count = DIV_ROUND_UP(len, STM32_DMA3_MAX_BLOCK_SIZE);

	count = stm32_dma3_get_ll_count(chan, len);



	swdesc = stm32_dma3_chan_desc_alloc(chan, count);

	if (!swdesc)
@@ -1177,6 +1196,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha 
		remaining = len - offset;

		next_size = min_t(size_t, remaining, STM32_DMA3_MAX_BLOCK_SIZE);



		if (next_size < STM32_DMA3_MAX_BLOCK_SIZE && next_size >= chan->max_burst)

			next_size = chan->max_burst * (remaining / chan->max_burst);



		ret = stm32_dma3_chan_prep_hw(chan, DMA_MEM_TO_MEM, &swdesc->ccr, &ctr1, &ctr2,

					      src + offset, dst + offset, next_size);

		if (ret)
@@ -1215,12 +1237,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan 
	u32 i, j, count, ctr1, ctr2;

	int ret;



	count = sg_len;

	for_each_sg(sgl, sg, sg_len, i) {

		len = sg_dma_len(sg);

		if (len > STM32_DMA3_MAX_BLOCK_SIZE)

			count += DIV_ROUND_UP(len, STM32_DMA3_MAX_BLOCK_SIZE) - 1;

	}

	count = 0;

	for_each_sg(sgl, sg, sg_len, i)

		count += stm32_dma3_get_ll_count(chan, sg_dma_len(sg));



	swdesc = stm32_dma3_chan_desc_alloc(chan, count);

	if (!swdesc)
@@ -1237,6 +1256,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan 
		do {

			size_t chunk = min_t(size_t, len, STM32_DMA3_MAX_BLOCK_SIZE);



			if (chunk < STM32_DMA3_MAX_BLOCK_SIZE && chunk >= chan->max_burst)

				chunk = chan->max_burst * (len / chan->max_burst);



			if (dir == DMA_MEM_TO_DEV) {

				src = sg_addr;

				dst = dev_addr;
@@ -1269,6 +1291,10 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan 
		} while (len);

	}



	if (count != sg_len && chan->tcem != CTR2_TCEM_CHANNEL)

		dev_warn(chan2dev(chan), "Linked-list refactored, %d items instead of %d\n",

			 count, sg_len);



	/* Enable Error interrupts */

	swdesc->ccr |= CCR_USEIE | CCR_ULEIE | CCR_DTEIE;

	/* Enable Transfer state interrupts */