Unverified Commit cb5c2eb4 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown
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spi: microchip-core: Refactor FIFO read and write handlers 



Make both handlers to be shorter and easier to understand.
While at it, unify their style.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarPrajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Link: https://patch.msgid.link/20251127190031.2998705-3-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 545d1287

drivers/spi/spi-microchip-core-spi.c

+12 −19
Original line number Diff line number Diff line
@@ -97,15 +97,12 @@ static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi, u32 fifo_max 
		       MCHP_CORESPI_STATUS_RXFIFO_EMPTY)

			;



		/* On TX-only transfers always perform a dummy read */

		data = readb(spi->regs + MCHP_CORESPI_REG_RXDATA);

		if (spi->rx_buf)

			*spi->rx_buf++ = data;



		spi->rx_len--;

		if (!spi->rx_buf)

			continue;



		*spi->rx_buf = data;



		spi->rx_buf++;

	}

}
@@ -127,23 +124,19 @@ static void mchp_corespi_disable_ints(struct mchp_corespi *spi) 


static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 fifo_max)

{

	int i = 0;



	while ((i < fifo_max) &&

	       !(readb(spi->regs + MCHP_CORESPI_REG_STAT) &

		 MCHP_CORESPI_STATUS_TXFIFO_FULL)) {

		u32 word;



		word = spi->tx_buf ? *spi->tx_buf : 0xaa;

		writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA);

	for (int i = 0; i < fifo_max; i++) {

		if (readb(spi->regs + MCHP_CORESPI_REG_STAT) &

		    MCHP_CORESPI_STATUS_TXFIFO_FULL)

			break;



		/* On RX-only transfers always perform a dummy write */

		if (spi->tx_buf)

			spi->tx_buf++;

			writeb(*spi->tx_buf++, spi->regs + MCHP_CORESPI_REG_TXDATA);

		else

			writeb(0xaa, spi->regs + MCHP_CORESPI_REG_TXDATA);



		i++;

		spi->tx_len--;

	}



	spi->tx_len -= i;

}



static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)