Commit cbff0b1e authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-dsa-mv88e6xxx-further-ptp-related-cleanups' 

Russell King says:

====================
net: dsa: mv88e6xxx: further PTP-related cleanups

Further mv88e6xxx PTP-related cleanups, mostly centred around the
register definitions, but also moving one function prototype to a
more logical header.
====================

Link: https://patch.msgid.link/aMnJ1uRPvw82_aCT@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents e218ae40 e866e511

drivers/net/dsa/mv88e6xxx/hwtstamp.c

+1 −1
Original line number Diff line number Diff line
@@ -570,7 +570,7 @@ int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip) 
	}



	/* Set the ethertype of L2 PTP messages */

	err = mv88e6xxx_ptp_write(chip, MV88E6XXX_PTP_GC_ETYPE, ETH_P_1588);

	err = mv88e6xxx_ptp_write(chip, MV88E6XXX_PTP_ETHERTYPE, ETH_P_1588);

	if (err)

		return err;

drivers/net/dsa/mv88e6xxx/hwtstamp.h

+1 −0
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 
int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port,

			  struct kernel_ethtool_ts_info *info);



long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);

int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip);

void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip);

int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port);

drivers/net/dsa/mv88e6xxx/ptp.c

+12 −12
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ static u64 mv88e6352_ptp_clock_read(struct cyclecounter *cc) 
	u16 phc_time[2];

	int err;



	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time,

	err = mv88e6xxx_tai_read(chip, MV88E6352_TAI_TIME_LO, phc_time,

				 ARRAY_SIZE(phc_time));

	if (err)

		return 0;
@@ -158,7 +158,7 @@ static u64 mv88e6165_ptp_clock_read(struct cyclecounter *cc) 
	u16 phc_time[2];

	int err;



	err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time,

	err = mv88e6xxx_tai_read(chip, MV88E6165_PTP_GC_TIME_LO, phc_time,

				 ARRAY_SIZE(phc_time));

	if (err)

		return 0;
@@ -176,17 +176,17 @@ static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int rising) 
	u16 evcap_config;

	int err;



	evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE |

		       MV88E6XXX_TAI_CFG_CAP_CTR_START;

	evcap_config = MV88E6352_TAI_CFG_CAP_OVERWRITE |

		       MV88E6352_TAI_CFG_CAP_CTR_START;

	if (!rising)

		evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING;

		evcap_config |= MV88E6352_TAI_CFG_EVREQ_FALLING;



	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, evcap_config);

	err = mv88e6xxx_tai_write(chip, MV88E6352_TAI_CFG, evcap_config);

	if (err)

		return err;



	/* Write the capture config; this also clears the capture counter */

	return mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, 0);

	return mv88e6xxx_tai_write(chip, MV88E6352_TAI_EVENT_STATUS, 0);

}



static void mv88e6352_tai_event_work(struct work_struct *ugly)
@@ -199,7 +199,7 @@ static void mv88e6352_tai_event_work(struct work_struct *ugly) 
	int err;



	mv88e6xxx_reg_lock(chip);

	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS,

	err = mv88e6xxx_tai_read(chip, MV88E6352_TAI_EVENT_STATUS,

				 status, ARRAY_SIZE(status));

	mv88e6xxx_reg_unlock(chip);
@@ -207,19 +207,19 @@ static void mv88e6352_tai_event_work(struct work_struct *ugly) 
		dev_err(chip->dev, "failed to read TAI status register\n");

		return;

	}

	if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) {

	if (status[0] & MV88E6352_TAI_EVENT_STATUS_ERROR) {

		dev_warn(chip->dev, "missed event capture\n");

		return;

	}

	if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID))

	if (!(status[0] & MV88E6352_TAI_EVENT_STATUS_VALID))

		goto out;



	raw_ts = ((u32)status[2] << 16) | status[1];



	/* Clear the valid bit so the next timestamp can come in */

	status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID;

	status[0] &= ~MV88E6352_TAI_EVENT_STATUS_VALID;

	mv88e6xxx_reg_lock(chip);

	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]);

	err = mv88e6xxx_tai_write(chip, MV88E6352_TAI_EVENT_STATUS, status[0]);

	mv88e6xxx_reg_unlock(chip);

	if (err) {

		dev_err(chip->dev, "failed to write TAI status register\n");

drivers/net/dsa/mv88e6xxx/ptp.h

+25 −105
Original line number Diff line number Diff line
@@ -16,131 +16,56 @@ 
#include "chip.h"



/* Offset 0x00: TAI Global Config */

#define MV88E6XXX_TAI_CFG			0x00

#define MV88E6XXX_TAI_CFG_CAP_OVERWRITE		0x8000

#define MV88E6XXX_TAI_CFG_CAP_CTR_START		0x4000

#define MV88E6XXX_TAI_CFG_EVREQ_FALLING		0x2000

#define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO	0x1000

#define MV88E6XXX_TAI_CFG_IRL_ENABLE		0x0400

#define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN		0x0200

#define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN		0x0100

#define MV88E6XXX_TAI_CFG_TRIG_LOCK		0x0080

#define MV88E6XXX_TAI_CFG_BLOCK_UPDATE		0x0008

#define MV88E6XXX_TAI_CFG_MULTI_PTP		0x0004

#define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT	0x0002

#define MV88E6XXX_TAI_CFG_TRIG_ENABLE		0x0001

#define MV88E6352_TAI_CFG			0x00

#define MV88E6352_TAI_CFG_CAP_OVERWRITE		0x8000

#define MV88E6352_TAI_CFG_CAP_CTR_START		0x4000

#define MV88E6352_TAI_CFG_EVREQ_FALLING		0x2000

#define MV88E6352_TAI_CFG_TRIG_ACTIVE_LO	0x1000

#define MV88E6352_TAI_CFG_IRL_ENABLE		0x0400

#define MV88E6352_TAI_CFG_TRIG_IRQ_EN		0x0200

#define MV88E6352_TAI_CFG_EVREQ_IRQ_EN		0x0100

#define MV88E6352_TAI_CFG_TRIG_LOCK		0x0080

#define MV88E6352_TAI_CFG_BLOCK_UPDATE		0x0008

#define MV88E6352_TAI_CFG_MULTI_PTP		0x0004

#define MV88E6352_TAI_CFG_TRIG_MODE_ONESHOT	0x0002

#define MV88E6352_TAI_CFG_TRIG_ENABLE		0x0001



/* Offset 0x01: Timestamp Clock Period (ps) */

#define MV88E6XXX_TAI_CLOCK_PERIOD		0x01



/* Offset 0x02/0x03: Trigger Generation Amount */

#define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO	0x02

#define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI	0x03



/* Offset 0x04: Clock Compensation */

#define MV88E6XXX_TAI_TRIG_CLOCK_COMP		0x04



/* Offset 0x05: Trigger Configuration */

#define MV88E6XXX_TAI_TRIG_CFG			0x05



/* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */

#define MV88E6XXX_TAI_IRL_AMOUNT		0x06



/* Offset 0x07: Ingress Rate Limiter Compensation */

#define MV88E6XXX_TAI_IRL_COMP			0x07



/* Offset 0x08: Ingress Rate Limiter Compensation */

#define MV88E6XXX_TAI_IRL_COMP_PS		0x08



/* Offset 0x09: Event Status */

#define MV88E6XXX_TAI_EVENT_STATUS		0x09

#define MV88E6XXX_TAI_EVENT_STATUS_ERROR	0x0200

#define MV88E6XXX_TAI_EVENT_STATUS_VALID	0x0100

#define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK	0x00ff



/* Offset 0x0A/0x0B: Event Time */

#define MV88E6XXX_TAI_EVENT_TIME_LO		0x0a

#define MV88E6XXX_TAI_EVENT_TYPE_HI		0x0b

#define MV88E6352_TAI_EVENT_STATUS		0x09

#define MV88E6352_TAI_EVENT_STATUS_ERROR	0x0200

#define MV88E6352_TAI_EVENT_STATUS_VALID	0x0100

#define MV88E6352_TAI_EVENT_STATUS_CTR_MASK	0x00ff

/* Offset 0x0A/0x0B: Event Time Lo/Hi. Always read with Event Status. */



/* Offset 0x0E/0x0F: PTP Global Time */

#define MV88E6XXX_TAI_TIME_LO			0x0e

#define MV88E6XXX_TAI_TIME_HI			0x0f



/* Offset 0x10/0x11: Trig Generation Time */

#define MV88E6XXX_TAI_TRIG_TIME_LO		0x10

#define MV88E6XXX_TAI_TRIG_TIME_HI		0x11



/* Offset 0x12: Lock Status */

#define MV88E6XXX_TAI_LOCK_STATUS		0x12



/* Offset 0x00: Ether Type */

#define MV88E6XXX_PTP_GC_ETYPE			0x00

#define MV88E6352_TAI_TIME_LO			0x0e

#define MV88E6352_TAI_TIME_HI			0x0f



/* 6165 Global Control Registers */

/* Offset 0x00: Ether Type */

#define MV88E6XXX_PTP_GC_ETYPE			0x00



/* Offset 0x01: Message ID */

#define MV88E6XXX_PTP_GC_MESSAGE_ID		0x01



/* Offset 0x02: Time Stamp Arrive Time */

#define MV88E6XXX_PTP_GC_TS_ARR_PTR		0x02



/* Offset 0x03: Port Arrival Interrupt Enable */

#define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN	0x03



/* Offset 0x04: Port Departure Interrupt Enable */

#define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN	0x04



/* Offset 0x05: Configuration */

#define MV88E6XXX_PTP_GC_CONFIG			0x05

#define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE	BIT(1)

#define MV88E6XXX_PTP_GC_CONFIG_DIS_TS		BIT(0)



/* Offset 0x8: Interrupt Status */

#define MV88E6XXX_PTP_GC_INT_STATUS		0x08



/* Offset 0x9/0xa: Global Time */

#define MV88E6XXX_PTP_GC_TIME_LO		0x09

#define MV88E6XXX_PTP_GC_TIME_HI		0x0A

#define MV88E6165_PTP_GC_TIME_LO		0x09

#define MV88E6165_PTP_GC_TIME_HI		0x0A



/* 6165 Per Port Registers */

/* 6165 Per Port Registers. The arrival and departure registers are a

 * common block consisting of status, two time registers and the sequence ID

 */

/* Offset 0: Arrival Time 0 Status */

#define MV88E6165_PORT_PTP_ARR0_STS	0x00



/* Offset 0x01/0x02: PTP Arrival 0 Time */

#define MV88E6165_PORT_PTP_ARR0_TIME_LO	0x01

#define MV88E6165_PORT_PTP_ARR0_TIME_HI	0x02



/* Offset 0x03: PTP Arrival 0 Sequence ID */

#define MV88E6165_PORT_PTP_ARR0_SEQID	0x03



/* Offset 0x04: PTP Arrival 1 Status */

#define MV88E6165_PORT_PTP_ARR1_STS	0x04



/* Offset 0x05/0x6E: PTP Arrival 1 Time */

#define MV88E6165_PORT_PTP_ARR1_TIME_LO	0x05

#define MV88E6165_PORT_PTP_ARR1_TIME_HI	0x06



/* Offset 0x07: PTP Arrival 1 Sequence ID */

#define MV88E6165_PORT_PTP_ARR1_SEQID	0x07



/* Offset 0x08: PTP Departure Status */

#define MV88E6165_PORT_PTP_DEP_STS	0x08



/* Offset 0x09/0x0a: PTP Deperture Time */

#define MV88E6165_PORT_PTP_DEP_TIME_LO	0x09

#define MV88E6165_PORT_PTP_DEP_TIME_HI	0x0a



/* Offset 0x0b: PTP Departure Sequence ID */

#define MV88E6165_PORT_PTP_DEP_SEQID	0x0b



/* Offset 0x0d: Port Status */

#define MV88E6164_PORT_STATUS		0x0d



#ifdef CONFIG_NET_DSA_MV88E6XXX_PTP



long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);

int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);

void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
@@ -153,11 +78,6 @@ extern const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops; 


#else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */



static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)

{

	return -1;

}



static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)

{

	return 0;