Commit cdd65e8b authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-7.1-2026-04-01' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-7.1-2026-04-01:

amdgpu:
- UserQ fixes
- PASID handling fix
- S4 fix for smu11 chips
- devcoredump fixes
- RAS fixes
- Misc small fixes
- DCN 4.2 updates
- DVI fixes
- DML fixes
- DC pipe validation fixes
- eDP DSC seamless boot
- DC FP rework
- swsmu cleanups
- GC 11.5.4 updates
- Add DC idle state manager
- Add support for using multiple engines for buffer fills and clears
- Misc SMU7 fixes

amdkfd:
- Non-4K page fixes
- Logging cleanups
- sysfs fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260401184456.3576660-1-alexander.deucher@amd.com
parents 9bdbf7eb 8b3e8fa6

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+245 −214
Original line number Diff line number Diff line
@@ -373,42 +373,24 @@ int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, 
	return -ENODEV;

}



int

amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,

int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev,

				  int *vram_width, int *vram_type,

				  int *vram_vendor)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index, i = 0;

	int index;

	u16 data_offset, size;

	union igp_info *igp_info;

	union vram_info *vram_info;

	union umc_info *umc_info;

	union vram_module *vram_module;

	u8 frev, crev;

	u8 mem_type;

	u8 mem_vendor;

	u32 mem_channel_number;

	u32 mem_channel_width;

	u32 module_id;



	if (adev->flags & AMD_IS_APU)

	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						    integratedsysteminfo);

	else {

		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

		case IP_VERSION(12, 0, 0):

		case IP_VERSION(12, 0, 1):

			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);

			break;

		default:

			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);

		}

	}

	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

					  index, &size,

					  &frev, &crev, &data_offset)) {

		if (adev->flags & AMD_IS_APU) {

		igp_info = (union igp_info *)

			(mode_info->atom_context->bios + data_offset);

		switch (frev) {
@@ -472,9 +454,30 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
			return -EINVAL;

		}

	} else {

			switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

			case IP_VERSION(12, 0, 0):

			case IP_VERSION(12, 0, 1):

		return -EINVAL;

	}

	return 0;

}



int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev,

				  int *vram_width, int *vram_type,

				  int *vram_vendor)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index;

	u16 data_offset, size;

	union umc_info *umc_info;

	u8 frev, crev;

	u8 mem_type;

	u8 mem_vendor;

	u32 mem_channel_number;

	u32 mem_channel_width;



	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);



	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

					  index, &size,

					  &frev, &crev, &data_offset)) {

		umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);



		if (frev == 4) {
@@ -494,10 +497,37 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
			default:

				return -EINVAL;

			}

				} else

		} else {

			return -EINVAL;

				break;

			default:

		}

	} else {

		return -EINVAL;

	}



	return 0;

}



int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,

				  int *vram_width, int *vram_type,

				  int *vram_vendor)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index, i = 0;

	u16 data_offset, size;

	union vram_info *vram_info;

	union vram_module *vram_module;

	u8 frev, crev;

	u8 mem_type;

	u8 mem_vendor;

	u32 mem_channel_number;

	u32 mem_channel_width;

	u32 module_id;



	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);



	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

					  index, &size,

					  &frev, &crev, &data_offset)) {

		vram_info = (union vram_info *)

			(mode_info->atom_context->bios + data_offset);
@@ -614,8 +644,9 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
			/* invalid frev */

			return -EINVAL;

		}

			}

		}



	} else {

		return -EINVAL;

	}



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

+4 −0
Original line number Diff line number Diff line
@@ -30,6 +30,10 @@ uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *ade 
bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);

int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev,

	int *vram_width, int *vram_type, int *vram_vendor);

int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev,

	int *vram_width, int *vram_type, int *vram_vendor);

int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,

	int *vram_width, int *vram_type, int *vram_vendor);

int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+2 −3
Original line number Diff line number Diff line
@@ -908,9 +908,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
			goto out_free_user_pages;



		amdgpu_bo_list_for_each_entry(e, p->bo_list) {

			/* One fence for TTM and one for each CS job */

			r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,

						 1 + p->gang_size);

						 TTM_NUM_MOVE_FENCES + p->gang_size);

			drm_exec_retry_on_contention(&p->exec);

			if (unlikely(r))

				goto out_free_user_pages;
@@ -920,7 +919,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 


		if (p->uf_bo) {

			r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,

						 1 + p->gang_size);

						 TTM_NUM_MOVE_FENCES + p->gang_size);

			drm_exec_retry_on_contention(&p->exec);

			if (unlikely(r))

				goto out_free_user_pages;

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c

+19 −6
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, 
void amdgpu_coredump_init(struct amdgpu_device *adev)

{

}

void amdgpu_coredump_fini(struct amdgpu_device *adev)

{

}

#else



#define AMDGPU_CORE_DUMP_SIZE_MAX (256 * 1024 * 1024)
@@ -192,12 +195,16 @@ static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev, 
	drm_printf(p, "VPE feature version: %u, fw version: 0x%08x\n",

		   adev->vpe.feature_version, adev->vpe.fw_version);



	if (adev->bios) {

		drm_printf(p, "\nVBIOS Information\n");

		drm_printf(p, "vbios name       : %s\n", ctx->name);

		drm_printf(p, "vbios pn         : %s\n", ctx->vbios_pn);

		drm_printf(p, "vbios version    : %d\n", ctx->version);

		drm_printf(p, "vbios ver_str    : %s\n", ctx->vbios_ver_str);

		drm_printf(p, "vbios date       : %s\n", ctx->date);

	}else {

		drm_printf(p, "\nVBIOS Information: NA\n");

	}

}



static ssize_t
@@ -436,4 +443,10 @@ void amdgpu_coredump_init(struct amdgpu_device *adev) 
{

	INIT_WORK(&adev->coredump_work, amdgpu_devcoredump_deferred_work);

}



void amdgpu_coredump_fini(struct amdgpu_device *adev)

{

	/* Finish deferred coredump formatting before HW/IP teardown. */

	flush_work(&adev->coredump_work);

}

#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h

+1 −0
Original line number Diff line number Diff line
@@ -50,4 +50,5 @@ struct amdgpu_coredump_info { 
void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,

		     bool vram_lost, struct amdgpu_job *job);

void amdgpu_coredump_init(struct amdgpu_device *adev);

void amdgpu_coredump_fini(struct amdgpu_device *adev);

#endif