Commit cdd9b2d7 authored by Cruise Hung's avatar Cruise Hung Committed by Alex Deucher
Browse files

drm/amd/display: Always update divider settings for DP tunnel 



[Why]
When transitioning from 640x480 at RBRx1 to HBR3x1,
both output pixel mode and pixel rate divider should update.
The needs_divider_update flag was only for 8b10b and 128b132b transition.

[How]
For DP tunneling, always update divider settings.

Reviewed-by: default avatarJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarCruise Hung <Cruise.Hung@amd.com>
Signed-off-by: default avatarMatthew Stewart <matthew.stewart2@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1758cf3c

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

+6 −1
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, 
	struct dc_state *state = link->dc->current_state;

	struct dc_stream_update stream_update = { 0 };

	bool dpms_off = false;

	bool needs_divider_update = false;

	bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);

	bool is_hpo_acquired;

	uint8_t count;
@@ -79,6 +80,10 @@ static void dp_retrain_link_dp_test(struct dc_link *link, 
	int num_streams_on_link = 0;

	struct dc *dc = (struct dc *)link->dc;



	needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=

		link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings))

		|| link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA;



	udelay(100);



	link_get_master_pipes_with_dpms_on(link, state, &count, pipes);
@@ -95,7 +100,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, 
		pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg);

	}



	if (link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {

	if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {

		link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,

				link_setting, count,

				*pipes, &audio_output[0]);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

+7 −4
Original line number Diff line number Diff line
@@ -2250,11 +2250,14 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, 
	int i;



#if defined(CONFIG_DRM_AMD_DC_FP)

	if (link->dc->hwss.calculate_pix_rate_divider) {

		for (i = 0; i < state->stream_count; i++)

			if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)

				link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);

	}



	for (i = 0; i < pipe_count; i++) {

		if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)

			link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);



		// Setup audio